[Intel-gfx] [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+

Chris Wilson chris at chris-wilson.co.uk
Wed Apr 17 07:09:07 UTC 2019

Quoting Ville Syrjala (2019-04-15 15:16:41)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Since SKL the eLLC has been sitting on the far side of the system
> agent, meaning the display engine can utilize it. Let's enable that.
> I chose WB for the caching mode, because my numbers are indicating
> that WT might actually be WB and WC might actually be UC. I'm not
> 100% sure that is indeed the case but at least my simple rendercopy
> based benchmark didn't see any difference in performance.
> Also if I configure things to do LLCeLLC+WT I still get cache dirt
> on my screen, suggesting that is in fact operating in WB mode
> anyway. This is also the reason I had to fix the MOCS target cache
> to really say PTE rather than LLC+eLLC.

We also need to check with hybrid setups that supply buffers via prime,
and we may need to end up marking those as explicitly uncached.

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