[Intel-gfx] [igt-dev] [PATCH i-g-t] i915: Update i915_drm.h
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Wed Apr 17 07:36:18 UTC 2019
On 17/04/2019 07:32, Chris Wilson wrote:
> Copy uapi/i915_drm.h across from
> kernel commit d1172ab3d443e84ade75285f8c107bfac7e386d8
> Author: Chris Wilson <chris at chris-wilson.co.uk>
> Date: Fri Apr 12 08:14:16 2019 +0100
>
> drm/i915: Introduce struct class_instance for engines across the uAPI
>
> and adapt gem_ctx_sseu to match the new struct.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
> include/drm-uapi/i915_drm.h | 191 +++++++++++++++++++++++++-----------
> tests/i915/gem_ctx_sseu.c | 26 ++---
> 2 files changed, 147 insertions(+), 70 deletions(-)
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 4ae1c6ff6..e01b3e1fd 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -62,6 +62,28 @@ extern "C" {
> #define I915_ERROR_UEVENT "ERROR"
> #define I915_RESET_UEVENT "RESET"
>
> +/*
> + * i915_user_extension: Base class for defining a chain of extensions
> + *
> + * Many interfaces need to grow over time. In most cases we can simply
> + * extend the struct and have userspace pass in more data. Another option,
> + * as demonstrated by Vulkan's approach to providing extensions for forward
> + * and backward compatibility, is to use a list of optional structs to
> + * provide those extra details.
> + *
> + * The key advantage to using an extension chain is that it allows us to
> + * redefine the interface more easily than an ever growing struct of
> + * increasing complexity, and for large parts of that interface to be
> + * entirely optional. The downside is more pointer chasing; chasing across
> + * the boundary with pointers encapsulated inside u64.
> + */
> +struct i915_user_extension {
> + __u64 next_extension;
> + __u32 name;
> + __u32 flags; /* All undefined bits must be zero. */
> + __u32 rsvd[4]; /* Reserved for future use; must be zero. */
> +};
> +
> /*
> * MOCS indexes used for GPU surfaces, defining the cacheability of the
> * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
> @@ -104,6 +126,18 @@ enum drm_i915_gem_engine_class {
> I915_ENGINE_CLASS_INVALID = -1
> };
>
> +/*
> + * There may be more than one engine fulfilling any role within the system.
> + * Each engine of a class is given a unique instance number and therefore
> + * any engine can be specified by its class:instance tuplet. APIs that allow
> + * access to any engine in the system will use struct i915_engine_class_instance
> + * for this identification.
> + */
> +struct i915_engine_class_instance {
> + __u16 engine_class; /* see enum drm_i915_gem_engine_class */
> + __u16 engine_instance;
> +};
> +
> /**
> * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
> *
> @@ -370,6 +404,7 @@ typedef struct _drm_i915_sarea {
> #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
> #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
> #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
> #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
> #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
> #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
> @@ -1421,65 +1456,17 @@ struct drm_i915_gem_wait {
> };
>
> struct drm_i915_gem_context_create {
> - /* output: id of new context*/
> - __u32 ctx_id;
> + __u32 ctx_id; /* output: id of new context*/
> __u32 pad;
> };
>
> -struct drm_i915_gem_context_destroy {
> - __u32 ctx_id;
> - __u32 pad;
> -};
> -
> -struct drm_i915_reg_read {
> - /*
> - * Register offset.
> - * For 64bit wide registers where the upper 32bits don't immediately
> - * follow the lower 32bits, the offset of the lower 32bits must
> - * be specified
> - */
> - __u64 offset;
> -#define I915_REG_READ_8B_WA (1ul << 0)
> -
> - __u64 val; /* Return value */
> -};
> -/* Known registers:
> - *
> - * Render engine timestamp - 0x2358 + 64bit - gen7+
> - * - Note this register returns an invalid value if using the default
> - * single instruction 8byte read, in order to workaround that pass
> - * flag I915_REG_READ_8B_WA in offset field.
> - *
> - */
> -
> -struct drm_i915_reset_stats {
> - __u32 ctx_id;
> - __u32 flags;
> -
> - /* All resets since boot/module reload, for all contexts */
> - __u32 reset_count;
> -
> - /* Number of batches lost when active in GPU, for this context */
> - __u32 batch_active;
> -
> - /* Number of batches lost pending for execution, for this context */
> - __u32 batch_pending;
> -
> - __u32 pad;
> -};
> -
> -struct drm_i915_gem_userptr {
> - __u64 user_ptr;
> - __u64 user_size;
> +struct drm_i915_gem_context_create_ext {
> + __u32 ctx_id; /* output: id of new context*/
> __u32 flags;
> -#define I915_USERPTR_READ_ONLY 0x1
> -#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
> - /**
> - * Returned handle for the object.
> - *
> - * Object handles are nonzero.
> - */
> - __u32 handle;
> +#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
> +#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
> + (-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
> + __u64 extensions;
> };
>
> struct drm_i915_gem_context_param {
> @@ -1521,6 +1508,7 @@ struct drm_i915_gem_context_param {
> */
> #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
> /* Must be kept compact -- no holes and well documented */
> +
> __u64 value;
> };
>
> @@ -1549,8 +1537,7 @@ struct drm_i915_gem_context_param_sseu {
> /*
> * Engine class & instance to be configured or queried.
> */
> - __u16 engine_class;
> - __u16 engine_instance;
> + struct i915_engine_class_instance engine;
>
> /*
> * Unused for now. Must be cleared to zero.
> @@ -1583,6 +1570,96 @@ struct drm_i915_gem_context_param_sseu {
> __u32 rsvd;
> };
>
> +struct drm_i915_gem_context_create_ext_setparam {
> +#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
> + struct i915_user_extension base;
> + struct drm_i915_gem_context_param param;
> +};
> +
> +struct drm_i915_gem_context_destroy {
> + __u32 ctx_id;
> + __u32 pad;
> +};
> +
> +/*
> + * DRM_I915_GEM_VM_CREATE -
> + *
> + * Create a new virtual memory address space (ppGTT) for use within a context
> + * on the same file. Extensions can be provided to configure exactly how the
> + * address space is setup upon creation.
> + *
> + * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
> + * returned in the outparam @id.
> + *
> + * No flags are defined, with all bits reserved and must be zero.
> + *
> + * An extension chain maybe provided, starting with @extensions, and terminated
> + * by the @next_extension being 0. Currently, no extensions are defined.
> + *
> + * DRM_I915_GEM_VM_DESTROY -
> + *
> + * Destroys a previously created VM id, specified in @id.
> + *
> + * No extensions or flags are allowed currently, and so must be zero.
> + */
> +struct drm_i915_gem_vm_control {
> + __u64 extensions;
> + __u32 flags;
> + __u32 vm_id;
> +};
> +
> +struct drm_i915_reg_read {
> + /*
> + * Register offset.
> + * For 64bit wide registers where the upper 32bits don't immediately
> + * follow the lower 32bits, the offset of the lower 32bits must
> + * be specified
> + */
> + __u64 offset;
> +#define I915_REG_READ_8B_WA (1ul << 0)
> +
> + __u64 val; /* Return value */
> +};
> +
> +/* Known registers:
> + *
> + * Render engine timestamp - 0x2358 + 64bit - gen7+
> + * - Note this register returns an invalid value if using the default
> + * single instruction 8byte read, in order to workaround that pass
> + * flag I915_REG_READ_8B_WA in offset field.
> + *
> + */
> +
> +struct drm_i915_reset_stats {
> + __u32 ctx_id;
> + __u32 flags;
> +
> + /* All resets since boot/module reload, for all contexts */
> + __u32 reset_count;
> +
> + /* Number of batches lost when active in GPU, for this context */
> + __u32 batch_active;
> +
> + /* Number of batches lost pending for execution, for this context */
> + __u32 batch_pending;
> +
> + __u32 pad;
> +};
> +
> +struct drm_i915_gem_userptr {
> + __u64 user_ptr;
> + __u64 user_size;
> + __u32 flags;
> +#define I915_USERPTR_READ_ONLY 0x1
> +#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> +};
> +
> enum drm_i915_oa_format {
> I915_OA_FORMAT_A13 = 1, /* HSW only */
> I915_OA_FORMAT_A29, /* HSW only */
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 3afa5c152..48e4411c8 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -144,23 +144,23 @@ static void test_engines(int fd)
>
> /* get_param */
>
> - sseu.engine_instance = -1; /* Assumed invalid. */
> + sseu.engine.engine_instance = -1; /* Assumed invalid. */
> igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
>
> - sseu.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
> + sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
> igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
>
> - sseu.engine_instance = 0; /* Class invalid. */
> + sseu.engine.engine_instance = 0; /* Class invalid. */
> igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
> - sseu.engine_class = I915_ENGINE_CLASS_RENDER;
> + sseu.engine.engine_class = I915_ENGINE_CLASS_RENDER;
>
> last_with_engines = -1;
> for (class = 0; class < ~0; class++) {
> for (instance = 0; instance < ~0; instance++) {
> int ret;
>
> - sseu.engine_class = class;
> - sseu.engine_instance = instance;
> + sseu.engine.engine_class = class;
> + sseu.engine.engine_instance = instance;
>
> ret = __gem_context_get_param(fd, &arg);
>
> @@ -182,19 +182,19 @@ static void test_engines(int fd)
> * Get some proper values before trying to reprogram them onto
> * an invalid engine.
> */
> - sseu.engine_class = 0;
> - sseu.engine_instance = 0;
> + sseu.engine.engine_class = 0;
> + sseu.engine.engine_instance = 0;
> gem_context_get_param(fd, &arg);
>
> /* set_param */
>
> - sseu.engine_instance = -1; /* Assumed invalid. */
> + sseu.engine.engine_instance = -1; /* Assumed invalid. */
> igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
>
> - sseu.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
> + sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
> igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
>
> - sseu.engine_instance = 0; /* Class invalid. */
> + sseu.engine.engine_instance = 0; /* Class invalid. */
> igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
>
> last_with_engines = -1;
> @@ -202,8 +202,8 @@ static void test_engines(int fd)
> for (instance = 0; instance < ~0; instance++) {
> int ret;
>
> - sseu.engine_class = class;
> - sseu.engine_instance = instance;
> + sseu.engine.engine_class = class;
> + sseu.engine.engine_instance = instance;
>
> ret = __gem_context_set_param(fd, &arg);
>
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Regards,
Tvrtko
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