[Intel-gfx] [PATCH v3 13/19] drm/i915/huc: New HuC status register for Gen11
Daniele Ceraolo Spurio
daniele.ceraolospurio at intel.com
Wed Apr 17 17:39:02 UTC 2019
On 4/16/19 10:39 PM, Michal Wajdeczko wrote:
> Gen11 defines new register for checking HuC authentication status.
> Look into the right register and bit.
>
> v2: use reg/mask/value instead of dedicated functions (Daniele)
>
> BSpec: 19686
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Tony Ye <tony.ye at intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
> Cc: John Spotswood <john.a.spotswood at intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_huc.c | 26 +++++++++++++++++++-------
> drivers/gpu/drm/i915/intel_huc.h | 6 ++++++
> 3 files changed, 28 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index d26de5193568..7eba65795b58 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -79,6 +79,9 @@
> #define HUC_STATUS2 _MMIO(0xD3B0)
> #define HUC_FW_VERIFIED (1<<7)
>
> +#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
> +#define HUC_LOAD_SUCCESSFUL (1 << 0)
> +
> #define GUC_WOPCM_SIZE _MMIO(0xc050)
> #define GUC_WOPCM_SIZE_LOCKED (1<<0)
> #define GUC_WOPCM_SIZE_SHIFT 12
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index 94c04f16a2ad..70042f108048 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -29,7 +29,19 @@
>
> void intel_huc_init_early(struct intel_huc *huc)
> {
> + struct drm_i915_private *i915 = huc_to_i915(huc);
> +
> intel_huc_fw_init_early(huc);
> +
> + if (INTEL_GEN(i915) >= 11) {
> + huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
> + huc->status.mask = HUC_LOAD_SUCCESSFUL;
> + huc->status.value = HUC_LOAD_SUCCESSFUL;
> + } else {
> + huc->status.reg = HUC_STATUS2;
> + huc->status.mask = HUC_FW_VERIFIED;
> + huc->status.value = HUC_FW_VERIFIED;
> + }
> }
>
> int intel_huc_init_misc(struct intel_huc *huc)
> @@ -56,7 +68,6 @@ int intel_huc_auth(struct intel_huc *huc)
> struct drm_i915_private *i915 = huc_to_i915(huc);
> struct intel_guc *guc = &i915->guc;
> struct i915_vma *vma;
> - u32 status;
> int ret;
>
> if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> @@ -80,12 +91,12 @@ int intel_huc_auth(struct intel_huc *huc)
>
> /* Check authentication status, it should be done by now */
> ret = __intel_wait_for_register(&i915->uncore,
> - HUC_STATUS2,
> - HUC_FW_VERIFIED,
> - HUC_FW_VERIFIED,
> - 2, 50, &status);
> + huc->status.reg,
> + huc->status.mask,
> + huc->status.value,
> + 2, 50, NULL);
> if (ret) {
> - DRM_ERROR("HuC: Firmware not verified %#x\n", status);
> + DRM_ERROR("HuC: Firmware not verified %d\n", ret);
> goto fail_unpin;
> }
>
> @@ -122,7 +133,8 @@ int intel_huc_check_status(struct intel_huc *huc)
> return -ENODEV;
>
> with_intel_runtime_pm(dev_priv, wakeref)
> - status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
> + status = (I915_READ(huc->status.reg) & huc->status.mask) ==
> + huc->status.value;
>
> return status;
> }
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> index 7e41d870b509..c539794e4bd4 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -25,6 +25,7 @@
> #ifndef _INTEL_HUC_H_
> #define _INTEL_HUC_H_
>
> +#include "i915_reg.h"
> #include "intel_uc_fw.h"
> #include "intel_huc_fw.h"
>
> @@ -33,6 +34,11 @@ struct intel_huc {
> struct intel_uc_fw fw;
>
> /* HuC-specific additions */
> + struct {
> + i915_reg_t reg;
> + u32 mask;
> + u32 value;
> + } status;
> };
>
> void intel_huc_init_early(struct intel_huc *huc);
>
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