[Intel-gfx] [RFC 6/8] drm/i915: Prefer passing intel_irq instead of intel_core
Rodrigo Vivi
rodrigo.vivi at intel.com
Thu Apr 18 20:53:45 UTC 2019
The plan is to convert most of arguments to use intel_irq
instead of intel_core or i915.
Note that dev_priv is not getting replaced by i915 because
the plan also include to move dev_priv to intel_irq.
The caveat is that we will need the uncore for tracking
the mmio region that we need, but at least code keeps "clean"
and less dependent on other components.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 238 ++++++++++++++++----------------
2 files changed, 122 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8368daecf478..f783d63b686f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -662,6 +662,8 @@ struct intel_irq {
};
u32 gt_mask;
u32 pipestat_mask[I915_MAX_PIPES];
+
+ struct intel_uncore *uncore;
};
struct intel_rps {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0468fbea70af..27cae1e7f2cc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -136,120 +136,120 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
};
-static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
+static void gen3_irq_reset(struct intel_irq *irq, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier)
{
- intel_uncore_write(uncore, imr, 0xffffffff);
- intel_uncore_posting_read(uncore, imr);
+ intel_uncore_write(irq->uncore, imr, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, imr);
- intel_uncore_write(uncore, ier, 0);
+ intel_uncore_write(irq->uncore, ier, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- intel_uncore_write(uncore, iir, 0xffffffff);
- intel_uncore_posting_read(uncore, iir);
- intel_uncore_write(uncore, iir, 0xffffffff);
- intel_uncore_posting_read(uncore, iir);
+ intel_uncore_write(irq->uncore, iir, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, iir);
+ intel_uncore_write(irq->uncore, iir, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, iir);
}
-static void gen2_irq_reset(struct intel_uncore *uncore)
+static void gen2_irq_reset(struct intel_irq *irq)
{
- intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IMR);
+ intel_uncore_write16(irq->uncore, GEN2_IMR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IMR);
- intel_uncore_write16(uncore, GEN2_IER, 0);
+ intel_uncore_write16(irq->uncore, GEN2_IER, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
}
-#define GEN8_IRQ_RESET_NDX(uncore, type, which) \
+#define GEN8_IRQ_RESET_NDX(irq, type, which) \
({ \
unsigned int which_ = which; \
- gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
+ gen3_irq_reset((irq), GEN8_##type##_IMR(which_), \
GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
})
-#define GEN3_IRQ_RESET(uncore, type) \
- gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
+#define GEN3_IRQ_RESET(irq, type) \
+ gen3_irq_reset((irq), type##IMR, type##IIR, type##IER)
-#define GEN2_IRQ_RESET(uncore) \
- gen2_irq_reset(uncore)
+#define GEN2_IRQ_RESET(irq) \
+ gen2_irq_reset(irq)
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
*/
-static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
+static void gen3_assert_iir_is_zero(struct intel_irq *irq, i915_reg_t reg)
{
- u32 val = intel_uncore_read(uncore, reg);
+ u32 val = intel_uncore_read(irq->uncore, reg);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
i915_mmio_reg_offset(reg), val);
- intel_uncore_write(uncore, reg, 0xffffffff);
- intel_uncore_posting_read(uncore, reg);
- intel_uncore_write(uncore, reg, 0xffffffff);
- intel_uncore_posting_read(uncore, reg);
+ intel_uncore_write(irq->uncore, reg, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, reg);
+ intel_uncore_write(irq->uncore, reg, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, reg);
}
-static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
+static void gen2_assert_iir_is_zero(struct intel_irq *irq)
{
- u16 val = intel_uncore_read16(uncore, GEN2_IIR);
+ u16 val = intel_uncore_read16(irq->uncore, GEN2_IIR);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
i915_mmio_reg_offset(GEN2_IIR), val);
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
}
-static void gen3_irq_init(struct intel_uncore *uncore,
+static void gen3_irq_init(struct intel_irq *irq,
i915_reg_t imr, u32 imr_val,
i915_reg_t ier, u32 ier_val,
i915_reg_t iir)
{
- gen3_assert_iir_is_zero(uncore, iir);
+ gen3_assert_iir_is_zero(irq, iir);
- intel_uncore_write(uncore, ier, ier_val);
- intel_uncore_write(uncore, imr, imr_val);
- intel_uncore_posting_read(uncore, imr);
+ intel_uncore_write(irq->uncore, ier, ier_val);
+ intel_uncore_write(irq->uncore, imr, imr_val);
+ intel_uncore_posting_read(irq->uncore, imr);
}
-static void gen2_irq_init(struct intel_uncore *uncore,
+static void gen2_irq_init(struct intel_irq *irq,
u32 imr_val, u32 ier_val)
{
- gen2_assert_iir_is_zero(uncore);
+ gen2_assert_iir_is_zero(irq);
- intel_uncore_write16(uncore, GEN2_IER, ier_val);
- intel_uncore_write16(uncore, GEN2_IMR, imr_val);
- intel_uncore_posting_read16(uncore, GEN2_IMR);
+ intel_uncore_write16(irq->uncore, GEN2_IER, ier_val);
+ intel_uncore_write16(irq->uncore, GEN2_IMR, imr_val);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IMR);
}
-#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
+#define GEN8_IRQ_INIT_NDX(irq, type, which, imr_val, ier_val) \
({ \
unsigned int which_ = which; \
- gen3_irq_init((uncore), \
+ gen3_irq_init((irq), \
GEN8_##type##_IMR(which_), imr_val, \
GEN8_##type##_IER(which_), ier_val, \
GEN8_##type##_IIR(which_)); \
})
-#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
- gen3_irq_init((uncore), \
+#define GEN3_IRQ_INIT(irq, type, imr_val, ier_val) \
+ gen3_irq_init((irq), \
type##IMR, imr_val, \
type##IER, ier_val, \
type##IIR)
-#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
- gen2_irq_init((uncore), imr_val, ier_val)
+#define GEN2_IRQ_INIT(irq, imr_val, ier_val) \
+ gen2_irq_init((irq), imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
@@ -3368,12 +3368,12 @@ static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv)
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
if (HAS_PCH_NOP(dev_priv))
return;
- GEN3_IRQ_RESET(uncore, SDE);
+ GEN3_IRQ_RESET(irq, SDE);
if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
I915_WRITE(SERR_INT, 0xffffffff);
@@ -3401,16 +3401,16 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
- GEN3_IRQ_RESET(uncore, GT);
+ GEN3_IRQ_RESET(irq, GT);
if (INTEL_GEN(dev_priv) >= 6)
- GEN3_IRQ_RESET(uncore, GEN6_PM);
+ GEN3_IRQ_RESET(irq, GEN6_PM);
}
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
@@ -3422,13 +3422,13 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, VLV_);
+ GEN3_IRQ_RESET(irq, VLV_);
dev_priv->irq.mask = ~0u;
}
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 pipestat_mask;
u32 enable_mask;
@@ -3454,7 +3454,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->irq.mask = ~enable_mask;
- GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq.mask, enable_mask);
+ GEN3_IRQ_INIT(irq, VLV_, dev_priv->irq.mask, enable_mask);
}
/* drm_dma.h hooks
@@ -3462,9 +3462,9 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
static void ironlake_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
- GEN3_IRQ_RESET(uncore, DE);
+ GEN3_IRQ_RESET(irq, DE);
if (IS_GEN(dev_priv, 7))
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -3495,18 +3495,18 @@ static void valleyview_irq_reset(struct drm_device *dev)
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
- GEN8_IRQ_RESET_NDX(uncore, GT, 0);
- GEN8_IRQ_RESET_NDX(uncore, GT, 1);
- GEN8_IRQ_RESET_NDX(uncore, GT, 2);
- GEN8_IRQ_RESET_NDX(uncore, GT, 3);
+ GEN8_IRQ_RESET_NDX(irq, GT, 0);
+ GEN8_IRQ_RESET_NDX(irq, GT, 1);
+ GEN8_IRQ_RESET_NDX(irq, GT, 2);
+ GEN8_IRQ_RESET_NDX(irq, GT, 3);
}
static void gen8_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
int pipe;
gen8_master_intr_disable(dev_priv->uncore.regs);
@@ -3519,11 +3519,11 @@ static void gen8_irq_reset(struct drm_device *dev)
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(irq, DE_PIPE, pipe);
- GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
- GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(irq, GEN8_PCU_);
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
@@ -3549,7 +3549,7 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
static void gen11_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
int pipe;
gen11_master_intr_disable(dev_priv->uncore.regs);
@@ -3564,22 +3564,22 @@ static void gen11_irq_reset(struct drm_device *dev)
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(irq, DE_PIPE, pipe);
- GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
- GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
- GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(irq, GEN11_DE_HPD_);
+ GEN3_IRQ_RESET(irq, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(irq, GEN8_PCU_);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- GEN3_IRQ_RESET(uncore, SDE);
+ GEN3_IRQ_RESET(irq, SDE);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
@@ -3592,7 +3592,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
}
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
+ GEN8_IRQ_INIT_NDX(irq, DE_PIPE, pipe,
dev_priv->irq.de_mask[pipe],
~dev_priv->irq.de_mask[pipe] | extra_ier);
@@ -3602,7 +3602,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
enum pipe pipe;
spin_lock_irq(&dev_priv->irq.lock);
@@ -3613,7 +3613,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
}
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(irq, DE_PIPE, pipe);
spin_unlock_irq(&dev_priv->irq.lock);
@@ -3624,14 +3624,14 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
static void cherryview_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
I915_WRITE(GEN8_MASTER_IRQ, 0);
POSTING_READ(GEN8_MASTER_IRQ);
gen8_gt_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(irq, GEN8_PCU_);
spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->irq.display_interrupts_enabled)
@@ -3903,7 +3903,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
else
mask = SDE_GMBUS_CPT;
- gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
+ gen3_assert_iir_is_zero(&dev_priv->irq, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
@@ -3916,7 +3916,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 pm_irqs, gt_irqs;
pm_irqs = gt_irqs = 0;
@@ -3935,7 +3935,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
}
- GEN3_IRQ_INIT(uncore, GT, dev_priv->irq.gt_mask, gt_irqs);
+ GEN3_IRQ_INIT(irq, GT, dev_priv->irq.gt_mask, gt_irqs);
if (INTEL_GEN(dev_priv) >= 6) {
/*
@@ -3948,14 +3948,14 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
}
dev_priv->irq.pm_imr = 0xffffffff;
- GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->irq.pm_imr, pm_irqs);
+ GEN3_IRQ_INIT(irq, GEN6_PM, dev_priv->irq.pm_imr, pm_irqs);
}
}
static int ironlake_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 display_mask, extra_mask;
if (INTEL_GEN(dev_priv) >= 7) {
@@ -3974,7 +3974,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
}
if (IS_HASWELL(dev_priv)) {
- gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(irq, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -3983,7 +3983,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
ibx_irq_pre_postinstall(dev);
- GEN3_IRQ_INIT(uncore, DE, dev_priv->irq.mask,
+ GEN3_IRQ_INIT(irq, DE, dev_priv->irq.mask,
display_mask | extra_mask);
gen5_gt_irq_postinstall(dev);
@@ -4054,7 +4054,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
/* These are interrupts we'll toggle with the ring mask register */
u32 gt_interrupts[] = {
@@ -4076,19 +4076,19 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->irq.pm_ier = 0x0;
dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
- GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
- GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
+ GEN8_IRQ_INIT_NDX(irq, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
+ GEN8_IRQ_INIT_NDX(irq, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled. Same wil be the case for GuC interrupts.
*/
- GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->irq.pm_imr, dev_priv->irq.pm_ier);
- GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
+ GEN8_IRQ_INIT_NDX(irq, GT, 2, dev_priv->irq.pm_imr, dev_priv->irq.pm_ier);
+ GEN8_IRQ_INIT_NDX(irq, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
}
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
u32 de_pipe_enables;
@@ -4125,7 +4125,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(irq, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
for_each_pipe(dev_priv, pipe) {
@@ -4133,20 +4133,20 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
+ GEN8_IRQ_INIT_NDX(irq, DE_PIPE, pipe,
dev_priv->irq.de_mask[pipe],
de_pipe_enables);
}
- GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
- GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
+ GEN3_IRQ_INIT(irq, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
+ GEN3_IRQ_INIT(irq, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
if (INTEL_GEN(dev_priv) >= 11) {
u32 de_hpd_masked = 0;
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
GEN11_DE_TBT_HOTPLUG_MASK;
- GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
+ GEN3_IRQ_INIT(irq, GEN11_DE_HPD_, ~de_hpd_masked,
de_hpd_enables);
gen11_hpd_detection_setup(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
@@ -4210,7 +4210,7 @@ static void icp_irq_postinstall(struct drm_device *dev)
I915_WRITE(SDEIER, 0xffffffff);
POSTING_READ(SDEIER);
- gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
+ gen3_assert_iir_is_zero(&dev_priv->irq, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
icp_hpd_detection_setup(dev_priv);
@@ -4219,7 +4219,7 @@ static void icp_irq_postinstall(struct drm_device *dev)
static int gen11_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
@@ -4228,7 +4228,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
gen11_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(irq, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
@@ -4258,17 +4258,17 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
static void i8xx_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
i9xx_pipestat_irq_reset(dev_priv);
- GEN2_IRQ_RESET(uncore);
+ GEN2_IRQ_RESET(irq);
}
static int i8xx_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u16 enable_mask;
I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4286,7 +4286,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- GEN2_IRQ_INIT(uncore, dev_priv->irq.mask, enable_mask);
+ GEN2_IRQ_INIT(irq, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4422,7 +4422,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
static void i915_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
if (I915_HAS_HOTPLUG(dev_priv)) {
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
@@ -4431,13 +4431,13 @@ static void i915_irq_reset(struct drm_device *dev)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, GEN2_);
+ GEN3_IRQ_RESET(irq, GEN2_);
}
static int i915_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 enable_mask;
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4464,7 +4464,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
dev_priv->irq.mask &= ~I915_DISPLAY_PORT_INTERRUPT;
}
- GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask);
+ GEN3_IRQ_INIT(irq, GEN2_, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4535,20 +4535,20 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
static void i965_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, GEN2_);
+ GEN3_IRQ_RESET(irq, GEN2_);
}
static int i965_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 enable_mask;
u32 error_mask;
@@ -4586,7 +4586,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
if (IS_G4X(dev_priv))
enable_mask |= I915_BSD_USER_INTERRUPT;
- GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask);
+ GEN3_IRQ_INIT(irq, GEN2_, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4698,6 +4698,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (IS_I945GM(dev_priv))
i945gm_vblank_work_init(dev_priv);
+ dev_priv->irq.uncore = &dev_priv->uncore;
+
intel_hpd_init_work(dev_priv);
INIT_WORK(&rps->work, gen6_pm_rps_work);
--
2.20.1
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