[Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Check deps along implicit inter-engine semaphores

Chris Wilson chris at chris-wilson.co.uk
Wed Apr 24 15:39:36 UTC 2019


Given an implicit semaphore from one engine to the next, check that if
we skip the wait on that semaphore the following batch although
submitted early (as it depends along the single engine timeline) is not
executed ahead of its dependency.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Cc: Matthew Brost <matthew.brost at intel.com>
---
 tests/i915/gem_exec_schedule.c | 72 ++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 3590b739a..5e18561d4 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -603,6 +603,76 @@ static void semaphore_resolve(int i915)
 	gem_context_destroy(i915, outer);
 }
 
+static void semaphore_noskip(int i915)
+{
+	unsigned int engine, other;
+	uint32_t ctx;
+
+	igt_assert(intel_get_drm_devid(i915) >= 8);
+
+	ctx = gem_context_create(i915);
+
+	for_each_physical_engine(i915, engine) {
+	for_each_physical_engine(i915, other) {
+		struct drm_i915_gem_exec_object2 obj[3];
+		struct drm_i915_gem_execbuffer2 eb;
+		igt_spin_t *chain, *spin;
+		uint32_t handle, cancel;
+		uint32_t *cs, *map;
+
+		if (other == engine || !gem_can_store_dword(i915, other))
+			continue;
+
+		chain = __igt_spin_new(i915, .engine = engine);
+
+		spin = __igt_spin_new(i915, .engine = other);
+		igt_spin_end(spin); /* we just want its address for later */
+		gem_sync(i915, spin->handle);
+		igt_spin_reset(spin);
+
+		handle = gem_create(i915, 4096);
+		cs = map = gem_mmap__cpu(i915, handle, 0, 4096, PROT_WRITE);
+
+		/* Cancel the following spinner */
+		*cs++ = MI_STORE_DWORD_IMM;
+		*cs++ = spin->obj[1].offset + offset_in_page(spin->condition);
+		*cs++ = 0;
+		*cs++ = MI_BATCH_BUFFER_END;
+
+		*cs++ = MI_BATCH_BUFFER_END;
+		munmap(map, 4096);
+
+		memset(obj, 0, sizeof(obj));
+		obj[0] = chain->obj[1];
+		obj[1] = spin->obj[1];
+		obj[2].handle = handle;
+		memset(&eb, 0, sizeof(eb));
+		eb.buffer_count = 3;
+		eb.buffers_ptr = to_user_pointer(obj);
+		eb.rsvd1 = ctx;
+		gem_execbuf(i915, &eb);
+
+		memset(obj, 0, sizeof(obj));
+		obj[0].handle = handle;
+		obj[0].flags = EXEC_OBJECT_WRITE;
+		obj[1] = spin->obj[1];
+		memset(&eb, 0, sizeof(eb));
+		eb.buffer_count = 2;
+		eb.buffers_ptr = to_user_pointer(obj);
+		gem_execbuf(i915, &eb);
+
+		igt_spin_set_timeout(chain, NSEC_PER_SEC / 100);
+		gem_sync(i915, spin->handle); /* To hang unless cancel runs! */
+
+		gem_close(i915, handle);
+		igt_spin_free(i915, spin);
+		igt_spin_free(i915, chain);
+	}
+	}
+
+	gem_context_destroy(i915, ctx);
+}
+
 static void reorder(int fd, unsigned ring, unsigned flags)
 #define EQUAL 1
 {
@@ -1592,6 +1662,8 @@ igt_main
 			semaphore_codependency(fd);
 		igt_subtest("semaphore-resolve")
 			semaphore_resolve(fd);
+		igt_subtest("semaphore-noskip")
+			semaphore_noskip(fd);
 
 		igt_subtest("smoketest-all")
 			smoketest(fd, ALL_ENGINES, 30);
-- 
2.20.1



More information about the Intel-gfx mailing list