[Intel-gfx] [PATCH 14/45] drm/i915: Make engine_mask & num_engines static
Jani Nikula
jani.nikula at intel.com
Thu Apr 25 09:30:59 UTC 2019
On Thu, 25 Apr 2019, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> Having removed the urge to modify the engine_mask at runtime, we can
> promote the num_engines from a runtime calculation to a static and push
> it into the device_info tables.
\o/
Acked-by: Jani Nikula <jani.nikula at intel.com>
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Jani Nikula <jani.nikula at intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
> drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 4 +-
> drivers/gpu/drm/i915/i915_pci.c | 45 +++++++++----------
> drivers/gpu/drm/i915/intel_device_info.h | 3 +-
> .../gpu/drm/i915/selftests/i915_gem_context.c | 4 +-
> drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
> 7 files changed, 27 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 862cf1040f88..b2cd6c6785be 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -383,9 +383,6 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
> goto cleanup;
> }
>
> - RUNTIME_INFO(i915)->num_engines =
> - hweight32(INTEL_INFO(i915)->engine_mask);
> -
> i915_check_and_clear_faults(i915);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> index 7a4804c47466..2edeedb748ed 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> @@ -1568,7 +1568,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
> struct intel_engine_cs *engine = rq->engine;
> enum intel_engine_id id;
> const int num_engines =
> - IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0;
> + IS_HSW_GT1(i915) ? INTEL_INFO(i915)->num_engines - 1 : 0;
> bool force_restore = false;
> int len;
> u32 *cs;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index 84538f69185b..6f223f7facde 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -1185,7 +1185,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
>
> pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n",
> count, flags,
> - RUNTIME_INFO(smoke->i915)->num_engines, smoke->ncontext);
> + INTEL_INFO(smoke->i915)->num_engines, smoke->ncontext);
> return 0;
> }
>
> @@ -1213,7 +1213,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
>
> pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n",
> count, flags,
> - RUNTIME_INFO(smoke->i915)->num_engines, smoke->ncontext);
> + INTEL_INFO(smoke->i915)->num_engines, smoke->ncontext);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index ffa2ee70a03d..431a4a2c20e1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -35,6 +35,7 @@
>
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
> +#define ENGINES(x) .engine_mask = (x), .num_engines = hweight8(x)
>
> #define I845_PIPE_OFFSETS \
> .pipe_offsets = { \
> @@ -145,6 +146,7 @@
>
> #define I830_FEATURES \
> GEN(2), \
> + ENGINES(BIT(RCS0)), \
> .is_mobile = 1, \
> .num_pipes = 2, \
> .display.has_overlay = 1, \
> @@ -154,7 +156,6 @@
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> .unfenced_needs_alignment = 1, \
> - .engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> I9XX_PIPE_OFFSETS, \
> @@ -164,6 +165,7 @@
>
> #define I845_FEATURES \
> GEN(2), \
> + ENGINES(BIT(RCS0)), \
> .num_pipes = 1, \
> .display.has_overlay = 1, \
> .display.overlay_needs_physical = 1, \
> @@ -171,7 +173,6 @@
> .gpu_reset_clobbers_display = true, \
> .hws_needs_physical = 1, \
> .unfenced_needs_alignment = 1, \
> - .engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> I845_PIPE_OFFSETS, \
> @@ -202,10 +203,10 @@ static const struct intel_device_info intel_i865g_info = {
>
> #define GEN3_FEATURES \
> GEN(3), \
> + ENGINES(BIT(RCS0)), \
> .num_pipes = 2, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> - .engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> I9XX_PIPE_OFFSETS, \
> @@ -286,11 +287,11 @@ static const struct intel_device_info intel_pineview_m_info = {
>
> #define GEN4_FEATURES \
> GEN(4), \
> + ENGINES(BIT(RCS0)), \
> .num_pipes = 2, \
> .display.has_hotplug = 1, \
> .display.has_gmch = 1, \
> .gpu_reset_clobbers_display = true, \
> - .engine_mask = BIT(RCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> I9XX_PIPE_OFFSETS, \
> @@ -320,25 +321,25 @@ static const struct intel_device_info intel_i965gm_info = {
> static const struct intel_device_info intel_g45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_G45),
> - .engine_mask = BIT(RCS0) | BIT(VCS0),
> + ENGINES(BIT(RCS0) | BIT(VCS0)),
> .gpu_reset_clobbers_display = false,
> };
>
> static const struct intel_device_info intel_gm45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_GM45),
> + ENGINES(BIT(RCS0) | BIT(VCS0)),
> .is_mobile = 1,
> .display.has_fbc = 1,
> .display.supports_tv = 1,
> - .engine_mask = BIT(RCS0) | BIT(VCS0),
> .gpu_reset_clobbers_display = false,
> };
>
> #define GEN5_FEATURES \
> GEN(5), \
> + ENGINES(BIT(RCS0) | BIT(VCS0)), \
> .num_pipes = 2, \
> .display.has_hotplug = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0), \
> .has_snoop = true, \
> .has_coherent_ggtt = true, \
> /* ilk does support rc6, but we do not implement [power] contexts */ \
> @@ -362,10 +363,10 @@ static const struct intel_device_info intel_ironlake_m_info = {
>
> #define GEN6_FEATURES \
> GEN(6), \
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0)), \
> .num_pipes = 2, \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> .has_rc6 = 1, \
> @@ -410,10 +411,10 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>
> #define GEN7_FEATURES \
> GEN(7), \
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0)), \
> .num_pipes = 3, \
> .display.has_hotplug = 1, \
> .display.has_fbc = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> .has_rc6 = 1, \
> @@ -468,6 +469,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
> static const struct intel_device_info intel_valleyview_info = {
> PLATFORM(INTEL_VALLEYVIEW),
> GEN(7),
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0)),
> .is_lp = 1,
> .num_pipes = 2,
> .has_runtime_pm = 1,
> @@ -479,7 +481,6 @@ static const struct intel_device_info intel_valleyview_info = {
> .ppgtt_size = 31,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
> .display_mmio_offset = VLV_DISPLAY_BASE,
> I9XX_PIPE_OFFSETS,
> I9XX_CURSOR_OFFSETS,
> @@ -489,7 +490,7 @@ static const struct intel_device_info intel_valleyview_info = {
>
> #define G75_FEATURES \
> GEN7_FEATURES, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0)), \
> .display.has_ddi = 1, \
> .has_fpga_dbg = 1, \
> .display.has_psr = 1, \
> @@ -553,18 +554,17 @@ static const struct intel_device_info intel_broadwell_rsvd_info = {
>
> static const struct intel_device_info intel_broadwell_gt3_info = {
> BDW_PLATFORM,
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)),
> .gt = 3,
> - .engine_mask =
> - BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> static const struct intel_device_info intel_cherryview_info = {
> PLATFORM(INTEL_CHERRYVIEW),
> GEN(8),
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0)),
> .num_pipes = 3,
> .display.has_hotplug = 1,
> .is_lp = 1,
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
> .has_64bit_reloc = 1,
> .has_runtime_pm = 1,
> .has_rc6 = 1,
> @@ -616,9 +616,7 @@ static const struct intel_device_info intel_skylake_gt2_info = {
>
> #define SKL_GT3_PLUS_PLATFORM \
> SKL_PLATFORM, \
> - .engine_mask = \
> - BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
> -
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1))
>
> static const struct intel_device_info intel_skylake_gt3_info = {
> SKL_GT3_PLUS_PLATFORM,
> @@ -632,9 +630,9 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>
> #define GEN9_LP_FEATURES \
> GEN(9), \
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0)), \
> .is_lp = 1, \
> .display.has_hotplug = 1, \
> - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
> .num_pipes = 3, \
> .has_64bit_reloc = 1, \
> .display.has_ddi = 1, \
> @@ -689,9 +687,8 @@ static const struct intel_device_info intel_kabylake_gt2_info = {
>
> static const struct intel_device_info intel_kabylake_gt3_info = {
> KBL_PLATFORM,
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)),
> .gt = 3,
> - .engine_mask =
> - BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> #define CFL_PLATFORM \
> @@ -710,9 +707,8 @@ static const struct intel_device_info intel_coffeelake_gt2_info = {
>
> static const struct intel_device_info intel_coffeelake_gt3_info = {
> CFL_PLATFORM,
> + ENGINES(BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)),
> .gt = 3,
> - .engine_mask =
> - BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
> };
>
> #define GEN10_FEATURES \
> @@ -754,15 +750,14 @@ static const struct intel_device_info intel_cannonlake_info = {
> static const struct intel_device_info intel_icelake_11_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ICELAKE),
> - .engine_mask =
> - BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + ENGINES(BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2)),
> };
>
> static const struct intel_device_info intel_elkhartlake_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ELKHARTLAKE),
> + ENGINES(BIT(RCS0) | BIT(BCS0) | BIT(VCS0)),
> .is_alpha_support = 1,
> - .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
> .ppgtt_size = 36,
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 5a2e17d6146b..0deda1efd37d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -149,6 +149,7 @@ struct intel_device_info {
> u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> intel_engine_mask_t engine_mask; /* Engines supported by the HW */
> + u8 num_engines;
>
> enum intel_platform platform;
>
> @@ -202,8 +203,6 @@ struct intel_runtime_info {
> u8 num_sprites[I915_MAX_PIPES];
> u8 num_scalers[I915_MAX_PIPES];
>
> - u8 num_engines;
> -
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index b62f005e4d50..43d014472ac6 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -1257,7 +1257,7 @@ static int igt_ctx_readonly(void *arg)
> }
> }
> pr_info("Submitted %lu dwords (across %u engines)\n",
> - ndwords, RUNTIME_INFO(i915)->num_engines);
> + ndwords, INTEL_INFO(i915)->num_engines);
>
> dw = 0;
> idx = 0;
> @@ -1586,7 +1586,7 @@ static int igt_vm_isolation(void *arg)
> count += this;
> }
> pr_info("Checked %lu scratch offsets across %d engines\n",
> - count, RUNTIME_INFO(i915)->num_engines);
> + count, INTEL_INFO(i915)->num_engines);
>
> out_rpm:
> intel_runtime_pm_put(i915, wakeref);
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
> index b60591531e4a..8fe9a43c99d9 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -1211,7 +1211,7 @@ static int live_breadcrumbs_smoketest(void *arg)
> num_fences += atomic_long_read(&t[id].num_fences);
> }
> pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n",
> - num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus);
> + num_waits, num_fences, INTEL_INFO(i915)->num_engines, ncpus);
>
> mutex_lock(&i915->drm.struct_mutex);
> ret = igt_live_test_end(&live) ?: ret;
--
Jani Nikula, Intel Open Source Graphics Center
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