[Intel-gfx] [PATCH v5 2/8] drm/i915: vgpu shared memory setup for pv optimization

[Xiaolin Zhang]

To enable vgpu pv features, we need to setup a shared memory page
which will be used for data exchange directly accessed between both
guest and backend i915 driver to avoid emulation trap cost.

guest i915 will allocate this page memory and then pass it's physical
address to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page meory without any trap cost with the
help form hyperviser's read guest gpa functionality.

guest i915 will send VGT_G2V_SHARED_PAGE_SETUP notification to host GVT
once shared memory setup finished.

the layout of the shared_page also defined as well in this patch which
is used for pv features implementation.

v0: RFC
v1: addressed RFC comment to move both shared_page_lock and shared_page
to i915_virtual_gpu structure
v2: packed i915_virtual_gpu structure
v3: added SHARED_PAGE_SETUP g2v notification for pv shared_page setup
v4: added intel_vgpu_setup_shared_page() in i915_vgpu_pv.c
v5: per engine desc data in shared memory

Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    |  4 +++-
 drivers/gpu/drm/i915/i915_pvinfo.h |  5 ++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 40 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_vgpu.h   | 20 +++++++++++++++++++
 4 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91a16b35..acf9035 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1244,7 +1244,9 @@ struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
 	u32 pv_caps;
-};
+	spinlock_t shared_page_lock[I915_NUM_ENGINES];
+	struct gvt_shared_page *shared_page;
+} __packed;
 
 /* used in computing the new watermarks state */
 struct intel_wm_config {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 619305a..4657bf7 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,7 @@ enum vgt_g2v_type {
 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+	VGT_G2V_SHARED_PAGE_SETUP,
 	VGT_G2V_MAX,
 };
 
@@ -110,7 +111,9 @@ struct vgt_if {
 
 	u32 pv_caps;
 
-	u32  rsv7[0x200 - 25];    /* pad to one page */
+	u64 shared_page_gpa;
+
+	u32  rsv7[0x200 - 27];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 7329f5a..da439b1 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -135,6 +135,9 @@ void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
 
 	for (i = 0; i < 4; i++)
 		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+
+	if (dev_priv->vgpu.shared_page)
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
 }
 
 static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -286,6 +289,38 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
  * i915 vgpu PV support for Linux
  */
 
+/*
+ * shared_page setup for VGPU PV features
+ */
+static int intel_vgpu_setup_shared_page(struct drm_i915_private *dev_priv)
+{
+	struct intel_uncore *uncore = &dev_priv->uncore;
+	u64 gpa;
+	int i;
+
+	dev_priv->vgpu.shared_page =  (struct gvt_shared_page *)
+			get_zeroed_page(GFP_KERNEL);
+	if (!dev_priv->vgpu.shared_page) {
+		DRM_ERROR("out of memory for shared page memory\n");
+		return -ENOMEM;
+	}
+
+	/* pass guest memory pa address to GVT and then read back to verify */
+	gpa = __pa(dev_priv->vgpu.shared_page);
+	__raw_uncore_write64(uncore, vgtif_reg(shared_page_gpa), gpa);
+	if (gpa != __raw_uncore_read64(uncore, vgtif_reg(shared_page_gpa))) {
+		DRM_ERROR("vgpu: passed shared_page_gpa failed\n");
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
+		return -EIO;
+	}
+	__raw_uncore_write32(uncore, vgtif_reg(g2v_notify),
+			VGT_G2V_SHARED_PAGE_SETUP);
+	for (i = 0; i < I915_NUM_ENGINES; i++)
+		spin_lock_init(&dev_priv->vgpu.shared_page_lock[i]);
+
+	return 0;
+}
+
 /**
  * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
  * @dev_priv: i915 device private
@@ -313,6 +348,11 @@ bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv)
 	if (!pvcaps)
 		return false;
 
+	if (intel_vgpu_setup_shared_page(dev_priv)) {
+		dev_priv->vgpu.pv_caps = 0;
+		return false;
+	}
+
 	__raw_uncore_write32(uncore, vgtif_reg(pv_caps), pvcaps);
 
 	return true;
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 91010fc..697c426 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -26,6 +26,26 @@
 
 #include "i915_pvinfo.h"
 
+/*
+ * A shared page(4KB) between gvt and VM, could be allocated by guest driver
+ * or a fixed location in PCI bar 0 region
+ */
+struct pv_ppgtt_update {
+	u64 pdp;
+	u64 start;
+	u64 length;
+	u32 cache_level;
+};
+
+struct pv_submission {
+	u64 descs[EXECLIST_MAX_PORTS];
+};
+
+struct gvt_shared_page {
+	struct pv_ppgtt_update pv_ppgtt;
+	struct pv_submission pv_elsp[I915_NUM_ENGINES];
+};
+
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
 bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);
-- 
2.7.4