[Intel-gfx] [PATCH] drm/i915: Fix bug for GeminiLake

[Maarten Lankhorst]

Op 29-04-2019 om 17:10 schreef Stanislav Lisovskiy:
> When CDCLK is as low as 79200, picture gets
> unstable, while DSI and DE pll values were
> confirmed to be correct.
> Limiting to 158400 as agreed with Ville.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ae40a8679314..2b23f8500362 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	    IS_VALLEYVIEW(dev_priv))
>  		min_cdclk = max(320000, min_cdclk);
>  
> +	/*
> +	 * On Geminilake once the CDCLK gets as low as 79200
> +	 * picture gets unstable, despite that values are
> +	 * correct for DSI PLL and DE PLL.
> +	 */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> +	    IS_GEMINILAKE(dev_priv))
> +		min_cdclk = max(158400, min_cdclk);
> +
>  	if (min_cdclk > dev_priv->max_cdclk_freq) {
>  		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
>  			      min_cdclk, dev_priv->max_cdclk_freq);

Hey,

With a bit of love to the commit's first line, I think this patch looks good. :)

Is this behavior documented somewhere?

~Maarten