[Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake

[Saarinen, Jani]

HI, 
> -----Original Message-----
> From: Lisovskiy, Stanislav
> Sent: tiistai 30. huhtikuuta 2019 11.01
> To: intel-gfx at lists.freedesktop.org; jani.nikula at linux.intel.com
> Cc: Saarinen, Jani <jani.saarinen at intel.com>; Peres, Martin
> <martin.peres at intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Corrupt DSI picture fix for GeminiLake
> 
> On Tue, 2019-04-30 at 10:43 +0300, Jani Nikula wrote:
> > On Tue, 30 Apr 2019, Stanislav Lisovskiy <
> > stanislav.lisovskiy at intel.com> wrote:
> > > Currently due to regression CI machine displays show corrupt
> > > picture.
> > > Problem is when CDCLK is as low as 79200, picture gets unstable,
> > > while DSI and DE pll values were confirmed to be correct.
> > > Limiting to 158400 as agreed with Ville.
> > >
> > > We could not come up with any better solution yet, as PLL divider
> > > values both for MIPI(DSI PLL) and CDCLK(DE PLL) are correct, however
> > > seems that due to some boundary conditions, when clocking is too low
> > > we get wrong timings for DSI display.
> > > Similar workaround exists for VLV though, so just took similar
> > > condition into use. At least that way GLK platform will start to be
> > > usable again, with current drm-tip.
> > >
> > > v2: Fixed commit subject as suggested.
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> > > Acked-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > Do we have a bugzilla link?
> >
> > BR,
> > Jani.
> 
> No, or at least I'm not aware of. I just got a machine from CI for investigation :) I
> guess it might be worth to create a bug for that.
> 
> 
> Martin: do we have a bug for CI GLK issue?
We did had some bugs, but not sure if those are related to this issue. 

> 
> -Stanislav
> 
> >
> >
> > > ---
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index ae40a8679314..2b23f8500362 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -2277,6 +2277,15 @@ int intel_crtc_compute_min_cdclk(const
> > > struct intel_crtc_state *crtc_state)
> > >  	    IS_VALLEYVIEW(dev_priv))
> > >  		min_cdclk = max(320000, min_cdclk);
> > >
> > > +	/*
> > > +	 * On Geminilake once the CDCLK gets as low as 79200
> > > +	 * picture gets unstable, despite that values are
> > > +	 * correct for DSI PLL and DE PLL.
> > > +	 */
> > > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> > > +	    IS_GEMINILAKE(dev_priv))
> > > +		min_cdclk = max(158400, min_cdclk);
> > > +
> > >  	if (min_cdclk > dev_priv->max_cdclk_freq) {
> > >  		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d
> kHz)\n",
> > >  			      min_cdclk, dev_priv->max_cdclk_freq);
> >
> >