[Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement gen11 flush including tile cache

[Chris Wilson]

Quoting Mika Kuoppala (2019-08-13 08:57:51)
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > Quoting Mika Kuoppala (2019-08-12 17:01:07)
> >> @@ -2829,7 +2887,10 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> >>         logical_ring_default_irqs(engine);
> >>  
> >>         if (engine->class == RENDER_CLASS) {
> >> -               engine->emit_flush = gen8_emit_flush_render;
> >> +               if (INTEL_GEN(engine->i915) >= 11)
> >> +                       engine->emit_flush = gen11_emit_flush_render;
> >> +               else
> >> +                       engine->emit_flush = gen8_emit_flush_render;
> >>                 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
> >
> > No fini breadcrumb flush?
> 
> Well there are room for cleaning there for sure. I admit to being
> a bit coward. I don't have an icelake and changing that would
> warrant quite amount of gem_concurrent_blt cycles.
> 
> If you can convince me that ci/bat will catch my mistakes,
> I could reconsider.

It's the vital one. Changing emit_flush will have no impact by itself...
-Chris