[Intel-gfx] [PATCH 1/3] drm/i915/icl: Implement gen11 flush including tile cache

[Chris Wilson]

Quoting Mika Kuoppala (2019-08-15 09:30:53)
> Add tile cache flushing for gen11. To relive us from the
> burden of previous obsolete workarounds, make a dedicated
> flush/invalidate callback for gen11.
> 
> To fortify an independent single flush, do post
> sync op as there are indications that without it
> we don't flush everything. This should also make this
> callback more readily usable in tgl (see l3 fabric flush).
> 
> v2: whitespacing
> 
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

The bits match to bspec, so going by name alone,
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris