[Intel-gfx] [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl

[Matt Roper]

On Thu, Aug 15, 2019 at 11:19:36PM +0100, Chris Wilson wrote:
> Quoting Matt Roper (2019-08-15 22:58:59)
> > From the bspec:
> > 
> >         "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> >         in Render Engine to a reserved value (0xFFFF_FFFF) such that the
> >         programmed value doesn’t match the render target surface address
> >         programmed. This would disable render engine from generating
> >         modify messages to FBC unit in display."
> > 
> > Bspec: 11388
> > Bspec: 33451
> > Cc: José Roberto de Souza <jose.souza at intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> >  drivers/gpu/drm/i915/i915_reg.h             | 1 +
> >  2 files changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 704ace01e7f5..29b50e2c0627 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >         /* allow headerless messages for preemptible GPGPU context */
> >         WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> >                           GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> > +
> > +       /* Wa_1604278689:icl,ehl */
> > +       wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> > +                          0, /* write-only register; skip validation */
> > +                          0xFFFFFFFF);
> > +       wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF);
> 
> It's part of the context?
> -Chris

The register definitions say "This Register is saved and restored as
part of Context" so I think so?  But that does seem to be different than
how we used to program this register back before commit b339088d8
("drm/i915: Don't write IVB_FBC_RT_BASE") so maybe I'm misinterpreting?


Matt

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795