[Intel-gfx] [PATCH 3/6] drm/i915: Move gmbus definitions out of i915_reg.h

[Lucas De Marchi]

On Thu, Aug 15, 2019 at 6:24 PM Daniele Ceraolo Spurio
<daniele.ceraolospurio at intel.com> wrote:
>
> They're not related to registers, so move them to the more appropriate
> intel_gmbus.h
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_gmbus.h | 22 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h            |  1 +
>  drivers/gpu/drm/i915/i915_reg.h            | 22 +---------------------
>  3 files changed, 24 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index d989085b8d22..b96212b85425 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -11,6 +11,28 @@
>  struct drm_i915_private;
>  struct i2c_adapter;
>
> +#define GMBUS_PIN_DISABLED     0
> +#define GMBUS_PIN_SSC          1
> +#define GMBUS_PIN_VGADDC       2
> +#define GMBUS_PIN_PANEL                3
> +#define GMBUS_PIN_DPD_CHV      3 /* HDMID_CHV */
> +#define GMBUS_PIN_DPC          4 /* HDMIC */
> +#define GMBUS_PIN_DPB          5 /* SDVO, HDMIB */
> +#define GMBUS_PIN_DPD          6 /* HDMID */
> +#define GMBUS_PIN_RESERVED     7 /* 7 reserved */
> +#define GMBUS_PIN_1_BXT                1 /* BXT+ (atom) and CNP+ (big core) */
> +#define GMBUS_PIN_2_BXT                2
> +#define GMBUS_PIN_3_BXT                3
> +#define GMBUS_PIN_4_CNP                4
> +#define GMBUS_PIN_9_TC1_ICP    9
> +#define GMBUS_PIN_10_TC2_ICP   10
> +#define GMBUS_PIN_11_TC3_ICP   11
> +#define GMBUS_PIN_12_TC4_ICP   12
> +#define GMBUS_PIN_13_TC5_TGP   13
> +#define GMBUS_PIN_14_TC6_TGP   14
> +
> +#define GMBUS_NUM_PINS 15 /* including 0 */
> +
>  int intel_gmbus_setup(struct drm_i915_private *dev_priv);
>  void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
>  bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c4406a60f3e4..c6722d54ccd5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -68,6 +68,7 @@
>  #include "display/intel_display_power.h"
>  #include "display/intel_dpll_mgr.h"
>  #include "display/intel_frontbuffer.h"
> +#include "display/intel_gmbus.h"

if it wasn't GMBUS_NUM_PINS we could include-what-you-use rather than
adding the include here.
Alternative would be to leave the GMBUS_NUM_PINS here, which would be
ugly. Or dynamically allocate
the array, that would deserve a more careful thought.

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>  #include "display/intel_opregion.h"
>
>  #include "gem/i915_gem_context_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 827795262d68..ea2f0fa2402d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3207,27 +3207,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   GMBUS_RATE_1MHZ      (3 << 8) /* reserved on Pineview */
>  #define   GMBUS_HOLD_EXT       (1 << 7) /* 300ns hold time, rsvd on Pineview */
>  #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
> -#define   GMBUS_PIN_DISABLED   0
> -#define   GMBUS_PIN_SSC                1
> -#define   GMBUS_PIN_VGADDC     2
> -#define   GMBUS_PIN_PANEL      3
> -#define   GMBUS_PIN_DPD_CHV    3 /* HDMID_CHV */
> -#define   GMBUS_PIN_DPC                4 /* HDMIC */
> -#define   GMBUS_PIN_DPB                5 /* SDVO, HDMIB */
> -#define   GMBUS_PIN_DPD                6 /* HDMID */
> -#define   GMBUS_PIN_RESERVED   7 /* 7 reserved */
> -#define   GMBUS_PIN_1_BXT      1 /* BXT+ (atom) and CNP+ (big core) */
> -#define   GMBUS_PIN_2_BXT      2
> -#define   GMBUS_PIN_3_BXT      3
> -#define   GMBUS_PIN_4_CNP      4
> -#define   GMBUS_PIN_9_TC1_ICP  9
> -#define   GMBUS_PIN_10_TC2_ICP 10
> -#define   GMBUS_PIN_11_TC3_ICP 11
> -#define   GMBUS_PIN_12_TC4_ICP 12
> -#define   GMBUS_PIN_13_TC5_TGP 13
> -#define   GMBUS_PIN_14_TC6_TGP 14
> -
> -#define   GMBUS_NUM_PINS       15 /* including 0 */
> +
>  #define GMBUS1                 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
>  #define   GMBUS_SW_CLR_INT     (1 << 31)
>  #define   GMBUS_SW_RDY         (1 << 30)
> --
> 2.22.0
>
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-- 
Lucas De Marchi