[Intel-gfx] [PATCH 00/39] Tiger Lake batch 3

Lucas De Marchi lucas.demarchi at intel.com
Fri Aug 16 08:04:24 UTC 2019

After switching to smaller series and getting the patches applied, it's
time to go with a bigger series again to get a bigger context of patches
coming. If needed I can split the series or delegate to the original
author to handle the reviews.

This should also give a warning-free driver load, so we can get CI up
and running. I ended up changing the patches and reordering them after I
didn't have the machine anymore, so I couldn't test the final state. But
I can do it soon.

I grouped the patches by context to make it easier to move them

Batch 3 contains:

  - DDIC is gone

  - PSR: some of these patches are already in other series, but I needed
    them here in order to solve dependencies. They can continue their
    review either here or in the other series José sent.

    After reviewing some of these patches before sending, my feeling
    is that they could use some squashing: we add per-transcoder-psr to
    later restrict it. Just having the register in the transcoder is
    more a sign of encapsulation than that we really allow them on any
    transcoder.  I know that some of these patches were sent before we
    even have Tiger Lake, but now that we do maybe we could refactor
    than to be more straight to the point. José, could you take a look
    on those?

  - Registers moving from DDI to transcoder (also the case for the PSR

  - Workarounds

  - Register state context and Render Context.

    Daniele: I added a "HACK" to your commit since we need to double
    check the spec

  - DisplayPort training sequence

  - Private PAT

  - Perf support

  - Format modifier changes in Gen12

Daniele Ceraolo Spurio (3):
  HACK: drm/i915/tgl: Gen12 render context size
  drm/i915/tgl: add Gen12 default indirect ctx offset
  drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (17):
  drm/i915/psr: Make PSR registers relative to transcoders
  drm/i915: Add transcoder restriction to PSR2
  drm/i915: Do not unmask PSR interruption in IRQ postinstall
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915/tgl: Change PSR2 transcoder restriction
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lionel Landwerlin (2):
  drm/i915/perf: add a parameter to control the size of OA buffer
  drm/i915/tgl: Add perf support on TGL

Lucas De Marchi (4):
  drm/i915/tgl: do not use DDIC
  drm/i915/tgl: Introduce initial Tiger Lake workarounds
  drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (8):
  drm/i915/tgl: Implement Wa_1406941453
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
  drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl: Report valid VDBoxes with SFC capability
  drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Updated Private PAT programming
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 193 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.c  | 108 +++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  21 ++
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 +++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 184 +++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 312 +++++++++-------
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 161 ++++++---
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  31 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  36 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  18 +-
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  27 +-
 drivers/gpu/drm/i915/i915_irq.c               |  54 ++-
 drivers/gpu/drm/i915/i915_perf.c              | 337 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               | 202 +++++++++--
 drivers/gpu/drm/i915/intel_device_info.c      |   3 +-
 drivers/gpu/drm/i915/intel_pm.c               |  19 +-
 drivers/gpu/drm/i915/oa/i915_oa_tgl.c         | 113 ++++++
 drivers/gpu/drm/i915/oa/i915_oa_tgl.h         |  17 +
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 include/uapi/drm/i915_drm.h                   |   7 +
 32 files changed, 1733 insertions(+), 337 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h


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