[Intel-gfx] [PATCH v2 31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap

[Lucas De Marchi]

From: Michel Thierry <michel.thierry at intel.com>

GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.

HSD: 399379
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Signed-off-by: Michel Thierry <michel.thierry at intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 1 +
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b..7719fadfe785 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -81,6 +81,7 @@
 #define   GT_DOORBELL_ENABLE		  (1<<0)
 
 #define GEN8_GTCR			_MMIO(0x4274)
+#define GEN12_GTCR			_MMIO(0xcee8)
 #define   GEN8_GTCR_INVALIDATE		  (1<<0)
 
 #define GUC_ARAT_C6DIS			_MMIO(0xA178)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6f6f0687d0bb..5cb9860cb02e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -131,9 +131,14 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
+	struct drm_i915_private *i915 = ggtt->vm.i915;
 
 	gen6_ggtt_invalidate(ggtt);
-	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+
+	if (INTEL_GEN(i915) >= 12)
+		intel_uncore_write_fw(uncore, GEN12_GTCR, GEN8_GTCR_INVALIDATE);
+	else
+		intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
-- 
2.21.0