[Intel-gfx] [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04

Srivatsa, Anusha anusha.srivatsa at intel.com
Mon Aug 19 18:07:47 UTC 2019



> -----Original Message-----
> From: De Marchi, Lucas
> Sent: Monday, August 19, 2019 11:04 AM
> To: Srivatsa, Anusha <anusha.srivatsa at intel.com>
> Cc: intel-gfx at lists.freedesktop.org; Souza, Jose <jose.souza at intel.com>
> Subject: Re: [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04
> 
> On Mon, Aug 19, 2019 at 10:55:56AM -0700, Anusha Srivatsa wrote:
> >
> >
> >> -----Original Message-----
> >> From: De Marchi, Lucas
> >> Sent: Saturday, August 17, 2019 2:38 AM
> >> To: intel-gfx at lists.freedesktop.org
> >> Cc: Souza, Jose <jose.souza at intel.com>; Srivatsa, Anusha
> >> <anusha.srivatsa at intel.com>
> >> Subject: [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04
> >>
> >> 2 important fixes:
> >>   - vblank counter is now working
> >>   - PSR1 is working
> >>
> >> Cc: Jose Souza <jose.souza at intel.com>
> >> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> >
> >Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> 
> thanks. Can you send the DMC firmware to the firmware repo?

On it.

Anusha 
> Lucas De Marchi
> 
> >> ---
> >>  drivers/gpu/drm/i915/intel_csr.c | 4 ++--
> >>  1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> >> b/drivers/gpu/drm/i915/intel_csr.c
> >> index 8279e72edf4c..546577e39b4e 100644
> >> --- a/drivers/gpu/drm/i915/intel_csr.c
> >> +++ b/drivers/gpu/drm/i915/intel_csr.c
> >> @@ -39,8 +39,8 @@
> >>
> >>  #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
> >>
> >> -#define TGL_CSR_PATH			"i915/tgl_dmc_ver2_03.bin"
> >> -#define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 3)
> >> +#define TGL_CSR_PATH			"i915/tgl_dmc_ver2_04.bin"
> >> +#define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 4)
> >>  #define TGL_CSR_MAX_FW_SIZE		0x6000
> >>  MODULE_FIRMWARE(TGL_CSR_PATH);
> >>
> >> --
> >> 2.21.0
> >


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