[Intel-gfx] [PATCH v2 23/40] drm/i915/tgl: Register state context definition for Gen12

[Chris Wilson]

Quoting Mika Kuoppala (2019-08-22 14:31:53)
> Lucas De Marchi <lucas.demarchi at intel.com> writes:
> > +static void gen8_init_reg_state(u32 *regs,
> > +                             struct intel_context *ce,
> > +                             struct intel_engine_cs *engine,
> > +                             struct intel_ring *ring)
> > +{
> > +     struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
> > +     bool rcs = engine->class == RENDER_CLASS;
> > +     u32 base = engine->mmio_base;
> > +
> > +     regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
> > +                              MI_LRI_FORCE_POSTED;
> 
> It could be better that the imm batch size would be contained
> in the actual helper which does it. But as this would change
> the imm sizes, let's not go there, atleast not yet until
> everything is green on CI.
> 
> But the confusion I have is with the virtual engines.
> According to comments the virtual engine reg state setup
> has to mimic the execlist one exactly. With this
> gen12/gen8 split, we break the symmetry. Do we
> need same split in there?

If the layout of the context image changes, yes we do as we just update
the register offsets in situ.
-Chris