[Intel-gfx] [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression
Matt Roper
matthew.d.roper at intel.com
Thu Aug 29 00:33:40 UTC 2019
On Fri, Aug 23, 2019 at 01:20:53AM -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
>
> Gen-12 decompression is supported with Y-tiled main surface. The CCS is
> linear and has 4 bits of data for each main surface cache line pair, a
> ratio of 1:256. Gen-12 display decompression is incompatible with buffers
> compressed by earlier GPUs, so make use of a new modifier to identify
> gen-12 compression. Another notable change is that decompression is
> supported on all planes except cursor and on all pipes. This patch adds
> decompression support for [A,X]BGR888 pixel formats.
>
> Bspec: 18437
For TGL I think you want to point at bspec #49252.
>
> v2: Fix checkpatch warnings (Lucas)
>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Daniel Vetter <daniel.vetter at intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 63 +++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_sprite.c | 23 ++++---
> 2 files changed, 71 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 109d4fd961c6..190adbffe055 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1912,6 +1912,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> if (color_plane == 1)
> return 128;
> /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + if (color_plane == 1)
> + return cpp;
If the CCS itself is linear, is there a reason we don't treat this the
way we normally treat linear surfaces (i.e., return intel_tile_size())?
> + /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> @@ -2045,6 +2049,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + return 4 * 4 * 1024;
This is correct, but is there a reason we don't just write it as 16 *
1024? The bspec says "must be 16KB aligned" so 16 * 1024 seems more
natural.
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> @@ -2242,7 +2248,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
>
> static bool is_surface_linear(u64 modifier, int color_plane)
> {
> - return modifier == DRM_FORMAT_MOD_LINEAR;
> + return modifier == DRM_FORMAT_MOD_LINEAR ||
> + (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
> }
>
> static u32 intel_adjust_aligned_offset(int *x, int *y,
> @@ -2429,6 +2436,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> return I915_TILING_X;
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return I915_TILING_Y;
> default:
> return I915_TILING_NONE;
> @@ -2449,7 +2457,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> * us a ratio of one byte in the CCS for each 8x16 pixels in the
> * main surface.
> */
> -static const struct drm_format_info ccs_formats[] = {
> +static const struct drm_format_info skl_ccs_formats[] = {
> { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> @@ -2460,6 +2468,24 @@ static const struct drm_format_info ccs_formats[] = {
> .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> };
>
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
> +};
> +
> static const struct drm_format_info *
> lookup_format_info(const struct drm_format_info formats[],
> int num_formats, u32 format)
> @@ -2480,8 +2506,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> switch (cmd->modifier[0]) {
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> - return lookup_format_info(ccs_formats,
> - ARRAY_SIZE(ccs_formats),
> + return lookup_format_info(skl_ccs_formats,
> + ARRAY_SIZE(skl_ccs_formats),
> + cmd->pixel_format);
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + return lookup_format_info(gen12_ccs_formats,
> + ARRAY_SIZE(gen12_ccs_formats),
> cmd->pixel_format);
> default:
> return NULL;
> @@ -2490,7 +2520,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
>
> bool is_ccs_modifier(u64 modifier)
> {
> - return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> + return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
>
> @@ -2659,7 +2690,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> int main_x, main_y;
> int ccs_x, ccs_y;
>
> - intel_tile_dims(fb, i, &tile_width, &tile_height);
> + if (!is_surface_linear(fb->modifier, i)) {
> + intel_tile_dims(fb, i, &tile_width, &tile_height);
> + } else {
> + tile_width = 64 / cpp;
> + tile_height = 1;
> + }
> +
> tile_width *= hsub;
> tile_height *= vsub;
>
> @@ -4053,6 +4090,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> + /* fall through */
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Yf_TILED:
> return PLANE_CTL_TILED_YF;
> @@ -9828,7 +9867,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
> case PLANE_CTL_TILED_Y:
> plane_config->tiling = I915_TILING_Y;
> if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
> + fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> + I915_FORMAT_MOD_Y_TILED_CCS;
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> @@ -15695,6 +15736,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> is_ccs_modifier(fb->modifier))
> stride_alignment *= 4;
>
> + /*
> + * The main surface pitch must be paded to a multiple of four
s/paded/padded/
> + * tile widths.
> + */
> + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
> + i == 0)
> + stride_alignment *= 4;
> +
It might be worth moving this into intel_fb_stride_alignment itself.
Matt
> if (fb->pitches[i] & (stride_alignment - 1)) {
> DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
> i, fb->pitches[i], stride_alignment);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 71dae3c2f9db..73d32017be89 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane,
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 surf_addr = plane_state->color_plane[color_plane].offset;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> + u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
> u32 aux_stride = skl_plane_stride(plane_state, 1);
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> @@ -588,8 +589,10 @@ skl_program_plane(struct intel_plane *plane,
> I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
> I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
> I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
> - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> - (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
> +
> + if (INTEL_GEN(dev_priv) < 12)
> + aux_dist |= aux_stride;
> + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
>
> if (icl_is_hdr_plane(dev_priv, plane_id)) {
> u32 cus_ctl = 0;
> @@ -1745,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> - fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
> DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
> return -EINVAL;
> }
> @@ -2157,7 +2161,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> -static const u64 gen12_plane_format_modifiers_noccs[] = {
> +static const u64 gen12_plane_format_modifiers_ccs[] = {
> + I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> I915_FORMAT_MOD_Y_TILED,
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
> @@ -2319,6 +2324,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> break;
> default:
> return false;
> @@ -2329,6 +2335,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_XBGR8888:
> case DRM_FORMAT_ARGB8888:
> case DRM_FORMAT_ABGR8888:
> + if (is_ccs_modifier(modifier))
> + return true;
> + /* fall through */
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
> @@ -2524,13 +2533,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> formats = skl_get_plane_formats(dev_priv, pipe,
> plane_id, &num_formats);
>
> + plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> if (INTEL_GEN(dev_priv) >= 12) {
> - /* TODO: Implement support for gen-12 CCS modifiers */
> - plane->has_ccs = false;
> - modifiers = gen12_plane_format_modifiers_noccs;
> + modifiers = gen12_plane_format_modifiers_ccs;
> plane_funcs = &gen12_plane_funcs;
> } else {
> - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> if (plane->has_ccs)
> modifiers = skl_plane_format_modifiers_ccs;
> else
> --
> 2.23.0
>
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--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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