[Intel-gfx] [PATCH 01/10] drm/i915/gvt: use intel uncore functions for forcewake register access

[Jani Nikula]

Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using
intel_uncore_read_fw() and intel_uncore_write_fw(), respectively.

No functional changes.

Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
Cc: Zhi Wang <zhi.a.wang at intel.com>
Cc: intel-gvt-dev at lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
 drivers/gpu/drm/i915/gvt/mmio_context.c | 19 ++++++++++++-------
 drivers/gpu/drm/i915/gvt/scheduler.c    |  9 ++++++---
 2 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index aaf15916d29a..7c76e7871beb 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -175,7 +175,8 @@ static void load_render_mocs(struct drm_i915_private *dev_priv)
 		offset.reg = regs[ring_id];
 		for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 			gen9_render_mocs.control_table[ring_id][i] =
-				I915_READ_FW(offset);
+				intel_uncore_read_fw(&dev_priv->uncore,
+						     offset);
 			offset.reg += 4;
 		}
 	}
@@ -183,7 +184,7 @@ static void load_render_mocs(struct drm_i915_private *dev_priv)
 	offset.reg = 0xb020;
 	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
 		gen9_render_mocs.l3cc_table[i] =
-			I915_READ_FW(offset);
+			intel_uncore_read_fw(&dev_priv->uncore, offset);
 		offset.reg += 4;
 	}
 	gen9_render_mocs.initialized = true;
@@ -427,7 +428,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
 			new_v = gen9_render_mocs.control_table[ring_id][i];
 
 		if (old_v != new_v)
-			I915_WRITE_FW(offset, new_v);
+			intel_uncore_write_fw(&dev_priv->uncore, offset,
+					      new_v);
 
 		offset.reg += 4;
 	}
@@ -445,7 +447,8 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
 				new_v = gen9_render_mocs.l3cc_table[i];
 
 			if (old_v != new_v)
-				I915_WRITE_FW(l3_offset, new_v);
+				intel_uncore_write_fw(&dev_priv->uncore,
+						      l3_offset, new_v);
 
 			l3_offset.reg += 4;
 		}
@@ -492,13 +495,15 @@ static void switch_mmio(struct intel_vgpu *pre,
 
 		// save
 		if (pre) {
-			vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
+			vgpu_vreg_t(pre, mmio->reg) = intel_uncore_read_fw(&dev_priv->uncore,
+								           mmio->reg);
 			if (mmio->mask)
 				vgpu_vreg_t(pre, mmio->reg) &=
 						~(mmio->mask << 16);
 			old_v = vgpu_vreg_t(pre, mmio->reg);
 		} else
-			old_v = mmio->value = I915_READ_FW(mmio->reg);
+			old_v = mmio->value = intel_uncore_read_fw(&dev_priv->uncore,
+								   mmio->reg);
 
 		// restore
 		if (next) {
@@ -526,7 +531,7 @@ static void switch_mmio(struct intel_vgpu *pre,
 				new_v = mmio->value;
 		}
 
-		I915_WRITE_FW(mmio->reg, new_v);
+		intel_uncore_write_fw(&dev_priv->uncore, mmio->reg, new_v);
 
 		trace_render_mmio(pre ? pre->id : 0,
 				  next ? next->id : 0,
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 5b2a7d072ec9..e7a2c76fcdce 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -217,11 +217,14 @@ static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
 	i915_reg_t reg;
 
 	reg = RING_INSTDONE(ring_base);
-	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
+	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore,
+									  reg);
 	reg = RING_ACTHD(ring_base);
-	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
+	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore,
+									  reg);
 	reg = RING_ACTHD_UDW(ring_base);
-	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
+	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = intel_uncore_read_fw(&dev_priv->uncore,
+									  reg);
 }
 
 static int shadow_context_status_change(struct notifier_block *nb,
-- 
2.20.1