[Intel-gfx] [PATCH 3/3] drm/i915: Try hard to bind the context

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> It is not acceptable for context pinning to fail with -ENOSPC as we
> should always be able to make space in the GGTT. The only reason we may
> fail is that other "temporary" context pins are reserving their space
> and we need to wait for an available slot.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/676
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 21 ++++++++++++++++++---
>  1 file changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 10b3d6d44045..7e20c6f62cd5 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1934,9 +1934,24 @@ int gen6_ppgtt_pin(struct i915_ppgtt *base)
>  	 * size. We allocate at the top of the GTT to avoid fragmentation.
>  	 */
>  	if (!atomic_read(&ppgtt->pin_count)) {
> -		err = i915_vma_pin(ppgtt->vma,
> -				   0, GEN6_PD_ALIGN,
> -				   PIN_GLOBAL | PIN_HIGH);
> +		do {
> +			struct i915_address_space *vm = ppgtt->vma->vm;
> +
> +			err = i915_vma_pin(ppgtt->vma,
> +					   0, GEN6_PD_ALIGN,
> +					   PIN_GLOBAL | PIN_HIGH);
> +			if (err != -ENOSPC)
> +				break;
> +
> +			/* We don't take no for an answer! */
> +			err = mutex_lock_interruptible(&vm->mutex);
> +			if (err == 0) {
> +				err = i915_gem_evict_vm(vm);

Why would we hold any significant amount of vmas?
I thought we need to kick the ggtt hard in order for this
to fit in.

-Mika

> +				mutex_unlock(&vm->mutex);
> +			}
> +			if (err)
> +				break;
> +		} while (1);
>  	}
>  	if (!err)
>  		atomic_inc(&ppgtt->pin_count);
> -- 
> 2.24.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx