[Intel-gfx] [PATCH 2/2] drm/i915/dp/tgl+: Update combo phy vswing tables

[Matt Roper]

On Mon, Dec 02, 2019 at 06:31:10PM -0800, José Roberto de Souza wrote:
> TGL has now a table for RBR and HBR and another table for HBR2 over
> combo phys. The HBR2 one has some small changes comparing to the ICL
> one, so adding two new tables and adding a function to return TGL
> combo phy tables.
> 
> BSpec: 49291
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 66 ++++++++++++++++++++++--
>  1 file changed, 62 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 914f0cc4d237..facf3dfa2a41 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -625,6 +625,34 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
>  	{ 0x0, 0x0, 0xA },	/* 10		Full	-3 dB */
>  };
>  
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x4F, 0x37, 0x00, 0x08 },	/* 350   500      3.1   */
> +	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
> +	{ 0x6, 0x7F, 0x2B, 0x00, 0x14 },	/* 350   900      8.2   */
> +	{ 0xA, 0x47, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xC, 0x63, 0x34, 0x00, 0x0B },	/* 500   700      2.9   */
> +	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */
> +	{ 0xC, 0x61, 0x3C, 0x00, 0x03 },	/* 650   700      0.6   */
> +	{ 0x6, 0x7B, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x4F, 0x37, 0x00, 0x08 },	/* 350   500      3.1   */
> +	{ 0xC, 0x71, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
> +	{ 0x6, 0x7D, 0x2B, 0x00, 0x14 },	/* 350   900      8.2   */
> +	{ 0xA, 0x4C, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xC, 0x73, 0x34, 0x00, 0x0B },	/* 500   700      2.9   */
> +	{ 0x6, 0x7F, 0x2F, 0x00, 0x10 },	/* 500   900      5.1   */
> +	{ 0xC, 0x6C, 0x3C, 0x00, 0x03 },	/* 650   700      0.6   */
> +	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};

Maybe switch the order of these two tables so HBR comes first and HBR2
comes second?  Doesn't really matter, but that will match the spec's
layout and also how we've ordered things in the past.

> +
>  static const struct ddi_buf_trans *
>  bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
>  {
> @@ -904,6 +932,32 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
>  	return icl_combo_phy_ddi_translations_dp_hbr2;
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +			int *n_entries)
> +{
> +	if (type == INTEL_OUTPUT_HDMI) {
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +		return icl_combo_phy_ddi_translations_hdmi;
> +	} else if (type == INTEL_OUTPUT_EDP) {
> +		if (rate > HBR2_RATE) {
> +			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> +			return icl_combo_phy_ddi_translations_edp_hbr3;
> +		} else if (dev_priv->vbt.edp.low_vswing) {
> +			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> +			return icl_combo_phy_ddi_translations_edp_hbr2;
> +		}
> +	}

Maybe it would be simpler to do

        if (type != INTEL_OUTPUT_DP)
                return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries);

rather than duplicating this if chain again?  Up to you.  Regardless,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> +
> +	if (rate > HBR_RATE) {
> +		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
> +		return tgl_combo_phy_ddi_translations_dp_hbr2;
> +	}
> +
> +	*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
> +	return tgl_combo_phy_ddi_translations_dp_hbr;
> +}
> +
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
> @@ -912,7 +966,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		if (intel_phy_is_combo(dev_priv, phy))
> -			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> +			tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
>  						0, &n_entries);
>  		else
>  			n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
> @@ -2373,7 +2427,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
>  		if (intel_phy_is_combo(dev_priv, phy))
> -			icl_get_combo_buf_trans(dev_priv, encoder->type,
> +			tgl_get_combo_buf_trans(dev_priv, encoder->type,
>  						intel_dp->link_rate, &n_entries);
>  		else
>  			n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
> @@ -2568,8 +2622,12 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>  	u32 n_entries, val;
>  	int ln;
>  
> -	ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> -						   &n_entries);
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate,
> +							   &n_entries);
> +	else
> +		ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> +							   &n_entries);
>  	if (!ddi_translations)
>  		return;
>  
> -- 
> 2.24.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795