[Intel-gfx] [CI] drm/i915/gt: Set vm again after MI_SET_CONTEXT

[Chris Wilson]

Reloading the PD after MI_SET_CONTEXT, along with copious amounts of
flushes, so far is making Baytrail more content.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 .../gpu/drm/i915/gt/intel_ring_submission.c   | 25 +++++++++++++++----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 5c22ca6f998a..336eb3f864c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1609,11 +1609,7 @@ static int switch_context(struct i915_request *rq)
 		 * post-sync op, this extra pass appears vital before a
 		 * mm switch!
 		 */
-		ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
-		if (ret)
-			return ret;
-
-		ret = flush_tlb(rq);
+		ret = rq->engine->emit_flush(rq, EMIT_FLUSH);
 		if (ret)
 			return ret;
 
@@ -1632,6 +1628,7 @@ static int switch_context(struct i915_request *rq)
 		ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
 		if (ret)
 			return ret;
+
 	}
 
 	if (ce->state) {
@@ -1645,6 +1642,24 @@ static int switch_context(struct i915_request *rq)
 			return ret;
 	}
 
+	if (vm) {
+		ret = rq->engine->emit_flush(rq, EMIT_FLUSH);
+		if (ret)
+			return ret;
+
+		ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm), PP_DIR_DCLV_2G);
+		if (ret)
+			return ret;
+
+		ret = flush_tlb(rq);
+		if (ret)
+			return ret;
+
+		ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+		if (ret)
+			return ret;
+	}
+
 	ret = remap_l3(rq);
 	if (ret)
 		return ret;
-- 
2.24.0