[Intel-gfx] [PATCH 3/3] drm/i915/icl: Cleanup combo PHY aux power well handlers

[Lucas De Marchi]

On Thu, Dec 12, 2019 at 02:37:35PM -0800, Matt Roper wrote:
>Now that the combo PHY aux power well handlers are used exclusively on
>Icelake, we can drop a bunch of the extra tests.  While we're at it,
>also switch these over to using intel_uncore_rmw() for the relevant
>register updates.

display/ shouldn't use intel_uncore_* yet as Jani has a series to
introduce intel_de_ (intel_display_ ?)

Lucas De Marchi

>
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> .../drm/i915/display/intel_display_power.c    | 40 ++++++++-----------
> 1 file changed, 16 insertions(+), 24 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 52f2332e0ab8..f02667a4e62b 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -418,31 +418,23 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> 	int pw_idx = power_well->desc->hsw.idx;
> 	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> 	u32 val;
>-	int wa_idx_max;
>+
>+	WARN_ON(!IS_ICELAKE(dev_priv));
>+	WARN_ON(intel_phy_is_combo(dev_priv, phy));
>
> 	val = I915_READ(regs->driver);
> 	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
>-	if (INTEL_GEN(dev_priv) < 12) {
>-		val = I915_READ(ICL_PORT_CL_DW12(phy));
>-		I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
>-	}
>+	intel_uncore_rmw(&dev_priv->uncore, ICL_PORT_CL_DW12(phy), 0,
>+			 ICL_LANE_ENABLE_AUX);
>
> 	hsw_wait_for_power_well_enable(dev_priv, power_well);
>
>-	/* Display WA #1178: icl, tgl */
>-	if (IS_TIGERLAKE(dev_priv))
>-		wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
>-	else
>-		wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
>-
>-	if (!IS_ELKHARTLAKE(dev_priv) &&
>-	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
>-	    !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
>-		val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
>-		val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
>-		I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
>-	}
>+	if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
>+	    !intel_bios_is_port_edp(dev_priv, (enum port)phy))
>+		intel_uncore_rmw(&dev_priv->uncore, ICL_AUX_ANAOVRD1(pw_idx), 0,
>+				 ICL_AUX_ANAOVRD1_ENABLE |
>+				 ICL_AUX_ANAOVRD1_LDO_BYPASS);
> }
>
> static void
>@@ -454,13 +446,13 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> 	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> 	u32 val;
>
>-	if (INTEL_GEN(dev_priv) < 12) {
>-		val = I915_READ(ICL_PORT_CL_DW12(phy));
>-		I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
>-	}
>+	WARN_ON(!IS_ICELAKE(dev_priv));
>+	WARN_ON(intel_phy_is_combo(dev_priv, phy));
>
>-	val = I915_READ(regs->driver);
>-	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
>+	intel_uncore_rmw(&dev_priv->uncore, ICL_PORT_CL_DW12(phy),
>+			 ICL_LANE_ENABLE_AUX, 0);
>+	intel_uncore_rmw(&dev_priv->uncore, regs->driver,
>+			 HSW_PWR_WELL_CTL_REQ(pw_idx), 0);
>
> 	hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>-- 
>2.23.0
>