[Intel-gfx] [PATCH 1/6] drm/i915/fbc: Reject PLANE_OFFSET.y%4!=0 on icl+ too

[Imre Deak]

On Fri, Dec 13, 2019 at 03:34:48PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> icl and tgl are still affected by the modulo 4 PLANE_OFFSET.y
> underrun issue. Reject such configurations on all gen9+ platforms.
> 
> Can be reproduced easily with the following sequence of
> hardware poking:
> while {
>   write FBC_CTL.enable=1
>   wait for vblank
> 
>   write PLANE_OFFSET .x=0 .y=32
>   write PLANE_SURF
>   wait for vblank
> 
>   # if PLANE_OFFSET.y is multiple of 4 the underrun won't happen
>   write PLANE_OFFSET .x=0 .y=31
>   write PLANE_SURF
>   wait for vblank
> 
>   # extra vblank wait is required here presumably
>   # to get FBC into the proper state
>   wait for vblank
> 
>   write FBC_CTL.enable=0
>   # underrun happens some time after FBC disable
>   wait for vblank
> }
> 
> Both 8888 and 565 pixel formats and all tilinga formats
> seem affected. Reproduced on KBL/GLK/ICL/TGL. BDW confirmed
> not affected.
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/792
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Imre Deak <imre.deak at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 6f1d5c032681..a1048ece541e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -776,7 +776,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  	 * having a Y offset that isn't divisible by 4 causes FIFO underrun
>  	 * and screen flicker.
>  	 */
> -	if (IS_GEN_RANGE(dev_priv, 9, 10) &&
> +	if (INTEL_GEN(dev_priv) >= 9 &&
>  	    (fbc->state_cache.plane.adjusted_y & 3)) {
>  		fbc->no_fbc_reason = "plane Y offset is misaligned";
>  		return false;
> -- 
> 2.23.0
> 
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