[Intel-gfx] [PATCH 14/15] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color

[Kahola, Mika]

On Wed, 2019-12-18 at 18:11 +0200, Imre Deak wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> 
> Gen12 display can decompress surfaces compressed by render engine
> with
> Clear Color, add a new modifier as the driver needs to know the
> surface
> was compressed by render engine.
> 
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
> v6: Documentation Nitpicks(Nanley)
> 
> Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally at intel.com>
> Cc: Rafael Antognolli <rafael.antognolli at intel.com>
> Cc: Nanley Chery <nanley.g.chery at intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> ---
>  include/uapi/drm/drm_fourcc.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h
> b/include/uapi/drm/drm_fourcc.h
> index 8bc0b31597d8..1c9c3991cab6 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,25 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL,
> 7)
>  
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for Gen-12
> render
> + * compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS
> is linear
> + * and at index 1. The clear color is stored at index 2, and the
> pitch should
> + * be ignored. The clear color structure is 256 bits. The first 128
> bits
> + * represents Raw Clear Color Red, Green, Blue and Alpha color each
> represented
> + * by 32 bits. The raw clear color is consumed by the 3d engine and
> generates
> + * the converted clear color of size 64 bits. The first 32 bits
> store the Lower
> + * Converted Clear Color value and the next 32 bits store the Higher
> Converted
> + * Clear Color value when applicable. The Converted Clear Color
> values are
> + * consumed by the DE. The last 64 bits are used to store Color
> Discard Enable
> + * and Depth Clear Value Valid which are ignored by the DE. A CCS
> cache line
> + * corresponds to an area of 4x1 tiles in the main surface. The main
> surface
> + * pitch is required to be a multiple of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized
> macroblocks
>   *