[Intel-gfx] [PATCH] drm/i915: Add Wa_1407352427:icl,ehl

[Lionel Landwerlin]

On 26/12/2019 19:46, Matt Roper wrote:
> The workaround database now indicates we need to disable psdunit clock
> gating as well.
>
> Bspec: 32354
> Bspec: 33450
> Bspec: 33451
> Suggested-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Atwood <matthew.s.atwood at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Acked-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>


I have the same question about applying this to stable kernels with ICL 
support :)


-Lionel


> ---
>   drivers/gpu/drm/i915/i915_reg.h | 3 +++
>   drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>   2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bbfedeb00b7f..b98734378c9a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4179,6 +4179,9 @@ enum {
>   #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
>   #define  VFUNIT_CLKGATE_DIS		(1 << 20)
>   
> +#define UNSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x94e4)
> +#define   PSDUNIT_CLKGATE_DIS		REG_BIT(5)
> +
>   #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
>   #define   CGPSF_CLKGATE_DIS		(1 << 3)
>   
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 31ec82337e4f..8bc8f0836368 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6590,6 +6590,10 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>   	/* WaEnable32PlaneMode:icl */
>   	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
>   		   _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> +
> +	/* Wa_1407352427:icl,ehl */
> +	intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
> +			 0, PSDUNIT_CLKGATE_DIS);
>   }
>   
>   static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)