[Intel-gfx] [PATCH] drm/i915: Engine relative MMIO

kbuild test robot lkp at intel.com
Sat Feb 23 09:27:17 UTC 2019


Hi John,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190222]
[cannot apply to v5.0-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/John-C-Harrison-Intel-com/drm-i915-Engine-relative-MMIO/20190223-131519
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-fedora-25 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/gvt/mmio_context.c: In function 'restore_context_mmio_for_inhibit':
>> drivers/gpu/drm/i915/gvt/mmio_context.c:202:10: error: implicit declaration of function 'MI_LOAD_REGISTER_IMM'; did you mean '__MI_LOAD_REGISTER_IMM'? [-Werror=implicit-function-declaration]
     *cs++ = MI_LOAD_REGISTER_IMM(count);
             ^~~~~~~~~~~~~~~~~~~~
             __MI_LOAD_REGISTER_IMM
   cc1: some warnings being treated as errors

vim +202 drivers/gpu/drm/i915/gvt/mmio_context.c

17865713 drivers/gpu/drm/i915/gvt/render.c       Zhi Wang  2016-05-01  179  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  180  static int
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  181  restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  182  				 struct i915_request *req)
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  183  {
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  184  	u32 *cs;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  185  	int ret;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  186  	struct engine_mmio *mmio;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  187  	struct intel_gvt *gvt = vgpu->gvt;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  188  	int ring_id = req->engine->id;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  189  	int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  190  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  191  	if (count == 0)
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  192  		return 0;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  193  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  194  	ret = req->engine->emit_flush(req, EMIT_BARRIER);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  195  	if (ret)
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  196  		return ret;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  197  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  198  	cs = intel_ring_begin(req, count * 2 + 2);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  199  	if (IS_ERR(cs))
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  200  		return PTR_ERR(cs);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  201  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23 @202  	*cs++ = MI_LOAD_REGISTER_IMM(count);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  203  	for (mmio = gvt->engine_mmio_list.mmio;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  204  	     i915_mmio_reg_valid(mmio->reg); mmio++) {
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  205  		if (mmio->ring_id != ring_id ||
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  206  		    !mmio->in_context)
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  207  			continue;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  208  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  209  		*cs++ = i915_mmio_reg_offset(mmio->reg);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  210  		*cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  211  				(mmio->mask << 16);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  212  		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  213  			      *(cs-2), *(cs-1), vgpu->id, ring_id);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  214  	}
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  215  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  216  	*cs++ = MI_NOOP;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  217  	intel_ring_advance(req, cs);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  218  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  219  	ret = req->engine->emit_flush(req, EMIT_BARRIER);
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  220  	if (ret)
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  221  		return ret;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  222  
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  223  	return 0;
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  224  }
cd7e61b9 drivers/gpu/drm/i915/gvt/mmio_context.c Weinan Li 2018-02-23  225  

:::::: The code at line 202 was first introduced by commit
:::::: cd7e61b93d068a80bfe6cb55bf00f17332d831a1 drm/i915/gvt: init mmio by lri command in vgpu inhibit context

:::::: TO: Weinan Li <weinan.z.li at intel.com>
:::::: CC: Zhenyu Wang <zhenyuw at linux.intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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