[Intel-gfx] [PATCH 06/11] drm/i915: Keep timeline HWSP allocated until idle across the system

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-02-27 10:44:42)
> 
> On 26/02/2019 10:23, Chris Wilson wrote:
> > In preparation for enabling HW semaphores, we need to keep in flight
> > timeline HWSP alive until its use across entire system has completed,
> > as any other timeline active on the GPU may still refer back to the
> > already retired timeline. We both have to delay recycling available
> > cachelines and unpinning old HWSP until the next idle point.
> > 
> > An easy option would be to simply keep all used HWSP until the system as
> > a whole was idle, i.e. we could release them all at once on parking.
> > However, on a busy system, we may never see a global idle point,
> > essentially meaning the resource will be leaked until we are forced to
> > do a GC pass. We already employ a fine-grained idle detection mechanism
> > for vma, which we can reuse here so that each cacheline can be freed
> > immediately after the last request using it is retired.
> > 
> > v3: Keep track of the activity of each cacheline.
> > v4: cacheline_free() on canceling the seqno tracking
> > v5: Finally with a testcase to exercise wraparound
> > v6: Pack cacheline into empty bits of page-aligned vaddr
> 
> Have you considered using page_(mask/unmask/pack/unpack)_bits helpers 
> instead of open coding it?

I forgot what they were called and was too lazy to read i915_utils.h
 
> Is the additional sharing of bits for two variables a thing which makes 
> it not as elegant?

Or the opposite: Do those wasted bits not stand out as being
inelegant? :)
-Chris