[Intel-gfx] [PATCH 4/6] drm/i915: always use INTEL_INFO() to access device info
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Wed Jan 2 09:58:05 UTC 2019
On 31/12/2018 14:56, Jani Nikula wrote:
> Hide the way device info is stored, in preparation of making device info
> a pointer to the const rodata in i915_pci.c. No functional changes.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 90 ++++++++++++++++++-------------------
> drivers/gpu/drm/i915/i915_reg.h | 12 ++---
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 4 files changed, 53 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 261932ee6837..8d7a3a852c10 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1636,7 +1636,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
> if (drm_debug & DRM_UT_DRIVER) {
> struct drm_printer p = drm_debug_printer("i915 device info:");
>
> - intel_device_info_dump(&dev_priv->info, &p);
> + intel_device_info_dump(INTEL_INFO(dev_priv), &p);
> intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4534beeed6f9..ce8d7a97e26b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2202,7 +2202,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
> #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
>
> -#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
> +#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
> #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
>
> #define REVID_FOREVER 0xff
> @@ -2215,11 +2215,11 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> /* Returns true if Gen is in inclusive range [Start, End] */
> #define IS_GEN_RANGE(dev_priv, s, e) \
> - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
> + (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
>
> #define IS_GEN(dev_priv, n) \
> (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
> - (dev_priv)->info.gen == (n))
> + INTEL_INFO(dev_priv)->gen == (n))
>
> /*
> * Return true if revision is in range [since,until] inclusive.
> @@ -2229,7 +2229,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_REVID(p, since, until) \
> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>
> -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
> +#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
>
> #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
> #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
> @@ -2251,7 +2251,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
> #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
> #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
> - (dev_priv)->info.gt == 1)
> + INTEL_INFO(dev_priv)->gt == 1)
> #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
> #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
> #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
> @@ -2263,7 +2263,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
> +#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
> @@ -2274,13 +2274,13 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
> - (dev_priv)->info.gt == 1)
> + INTEL_INFO(dev_priv)->gt == 1)
> /* ULX machines are also considered ULT. */
> #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
> INTEL_DEVID(dev_priv) == 0x0A1E)
> @@ -2303,21 +2303,21 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
> INTEL_DEVID(dev_priv) == 0x87C0)
> #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 2)
> + INTEL_INFO(dev_priv)->gt == 2)
> #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 4)
> + INTEL_INFO(dev_priv)->gt == 4)
> #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 2)
> + INTEL_INFO(dev_priv)->gt == 2)
> #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> - (dev_priv)->info.gt == 2)
> + INTEL_INFO(dev_priv)->gt == 2)
> #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
> - (dev_priv)->info.gt == 3)
> + INTEL_INFO(dev_priv)->gt == 3)
> #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>
> @@ -2390,27 +2390,27 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define ALL_ENGINES (~0)
>
> #define HAS_ENGINE(dev_priv, id) \
> - (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
> + (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
>
> #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
> #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
> #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
> #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
>
> -#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
> -#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
> +#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
> #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
> IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
>
> -#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
> +#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
>
> #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
> - ((dev_priv)->info.has_logical_ring_contexts)
> + (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
> #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
> - ((dev_priv)->info.has_logical_ring_elsq)
> + (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
> #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
> - ((dev_priv)->info.has_logical_ring_preemption)
> + (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
>
> #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>
> @@ -2424,12 +2424,12 @@ intel_info(const struct drm_i915_private *dev_priv)
>
> #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> GEM_BUG_ON((sizes) == 0); \
> - ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> + ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
> })
>
> -#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay)
> +#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
> #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
> - ((dev_priv)->info.display.overlay_needs_physical)
> + (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
>
> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
> @@ -2450,39 +2450,39 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
> !(IS_I915G(dev_priv) || \
> IS_I915GM(dev_priv)))
> -#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv)
> -#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug)
> +#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
> +#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
>
> #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> -#define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc)
> +#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
> #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
>
> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> -#define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst)
> +#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
>
> -#define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
> -#define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr)
> +#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
> +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
> +#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
>
> -#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
> -#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
> +#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
> +#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
> #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
>
> -#define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr)
> +#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
>
> -#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
> -#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
> +#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
> +#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
>
> -#define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc)
> +#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
>
> /*
> * For now, anything with a GuC requires uCode loading, and then supports
> * command submission once loaded. But these are logically independent
> * properties, so we have separate macros to test them.
> */
> -#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
> -#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
> +#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
> +#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
> #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
>
> @@ -2495,7 +2495,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
> #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
>
> -#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
> +#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> @@ -2535,12 +2535,12 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>
> -#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display)
> +#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch_display)
>
> #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
>
> /* DPF == dynamic parity feature */
> -#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
> +#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
> #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
> 2 : HAS_L3_DPF(dev_priv))
>
> @@ -3302,7 +3302,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
> static inline struct intel_device_info *
> mkwrite_device_info(struct drm_i915_private *dev_priv)
> {
> - return (struct intel_device_info *)&dev_priv->info;
> + return (struct intel_device_info *)INTEL_INFO(dev_priv);
> }
>
> /* modesetting */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index de1c9d495808..44958d994bfa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -185,14 +185,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> * Device info offset array based helpers for groups of registers with unevenly
> * spaced base offsets.
> */
> -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
> - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
> +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
> + INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
> DISPLAY_MMIO_BASE(dev_priv))
> -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
> - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
> +#define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
> + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
> DISPLAY_MMIO_BASE(dev_priv))
> -#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
> - dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
> +#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
> + INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
> DISPLAY_MMIO_BASE(dev_priv))
>
> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index e5e5c6e9ed28..fff468f17d2d 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2361,7 +2361,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
>
> bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
> {
> - return (dev_priv->info.has_reset_engine &&
> + return (INTEL_INFO(dev_priv)->has_reset_engine &&
> i915_modparams.reset >= 2);
> }
>
>
Looks OK.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Have you tried renaming the dev info member to see you got all of them?
Regards,
Tvrtko
More information about the Intel-gfx
mailing list