[Intel-gfx] [PATCH] drm/i915/gen6: Flush RING_IMR changes before changing the global GT IMR

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> On Baytail, notably, we can still detect missed interrupt syndrome
> (where we never spot a completed request). In this case, it can be
> alleviated by always keeping the interrupt unmasked, implying that the
> interrupt is being lost in the window after modifying the IMR. (This is
> the reason we still have the posting reads on enable_irq, if we remove
> them we miss interrupts!) Having narrowed the issue down to the IMR,
> rather than keeping it always enabled, applying the usual posting
> read/flush of the RING_IMR before unmasking the GT IMR also seems to
> prevent the missed interrupt. So be it.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8967dcb5f58f..3d5d6b908148 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -974,6 +974,10 @@ gen6_irq_enable(struct intel_engine_cs *engine)
>  	I915_WRITE_IMR(engine,
>  		       ~(engine->irq_enable_mask |
>  			 engine->irq_keep_mask));
> +
> +	/* Flush/delay to ensure the RING_IMR is active before the GT IMR */
> +	POSTING_READ_FW(RING_IMR(engine->mmio_base));
> +

I guess lifting this to be part of I915_WRITE_IMR would have caused
unwanted latencies on platforms that demonstratedly are free
of this sort of weirdness. I mean, the write should go in order
so the gpu view of events is consistent. Perhaps there
is some asyncness we can't grasp...or it is the delay like
the comment explains.

Acked-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

>  	gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
>  }
>  
> -- 
> 2.20.1
>
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