[Intel-gfx] Gen8+ engine-reset

Carlos Santa carlos.santa at intel.com
Sat Jan 5 02:39:53 UTC 2019

This is a rebased on the original patch series from Michel Thierry
that can be found here:


Note that this series is only limited to the GPU Watchdog timeout
for execlists as it leaves out support
for GuC based submission for a later time.

The series was also successfully tested from userspace through the
the Intel i965 media driver that is readily found on some
Linux based OS including Ubuntu OS and as well as Chromium OS. The
changes on the i965 media userspace driver are currently under review at


The testbed used on this series included a SKL-based NUC with 
2 BSD rings as well as a KBL-based Chromebook with a 1 BSD ring. 

Carlos Santa (1):
  drm/i915: Only process VCS2 only when supported

Michel Thierry (7):
  drm/i915: Add engine reset count in get-reset-stats ioctl
  drm/i915: Watchdog timeout: IRQ handler for gen8+
  drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+
  drm/i915: Watchdog timeout: DRM kernel interface to set the timeout
  drm/i915: Watchdog timeout: Include threshold value in error state
  drm/i915/watchdog: move emit_stop_watchdog until the very end of the
    ring commands
  drm/i915: Watchdog timeout: Blindly trust watchdog timeout for reset?

 drivers/gpu/drm/i915/i915_drv.h         |  56 +++++++
 drivers/gpu/drm/i915/i915_gem_context.c | 103 +++++++++++-
 drivers/gpu/drm/i915/i915_gem_context.h |   4 +
 drivers/gpu/drm/i915/i915_gpu_error.c   |  12 +-
 drivers/gpu/drm/i915/i915_gpu_error.h   |   5 +
 drivers/gpu/drm/i915/i915_irq.c         |  17 +-
 drivers/gpu/drm/i915/i915_reg.h         |   6 +
 drivers/gpu/drm/i915/intel_hangcheck.c  |  20 ++-
 drivers/gpu/drm/i915/intel_lrc.c        | 208 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_ringbuffer.h |  10 ++
 include/uapi/drm/i915_drm.h             |   7 +-
 11 files changed, 428 insertions(+), 20 deletions(-)


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