[Intel-gfx] [PATCH] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD

[Kenneth Graunke]

On Tuesday, January 8, 2019 7:53:05 AM PST Joonas Lahtinen wrote:
> + Ken/Jason for Mesa
> Quoting Matt Roper (2019-01-07 21:19:31)
> > On Mon, Jan 07, 2019 at 01:23:50PM +0100, Michał Winiarski wrote:
> > > On Mon, Jan 07, 2019 at 01:01:16PM +0200, Joonas Lahtinen wrote:
> > > > Quoting José Roberto de Souza (2019-01-04 19:37:00)
> > > > > According to Workaround database ICL also needs
> > > > > WaEnablePreemptionGranularityControlByUMD, to allow userspace to do
> > > > > fine-granularity preemptions per-context.
> > > > 
> > > > I must wonder where is the userspace component that needs this, and why
> > > > it hasn't been noticed earlier?
> > > > 
> > > > Or is this one more of the cases when no userspace actually uses the
> > > > register?
> > > 
> > > It's used:
> > > https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/mesa/drivers/dri/i965/brw_state_upload.c#L64
> > > 
> > > -Michał
> > 
> > Wasn't this just an artificial i915-only workaround that was added to
> > prevent breakage of pre-preemption UMD's?  Initial gen9 driver releases
> > didn't support preemption, so when preemption support did get added to
> > i915, the kernel had to force object-level off by default at context
> > creation to avoid breaking old userspace that didn't build batch buffers
> > with all the necessary preemption workarounds.  This CS_CHICKEN1
> > register was then exposed to userspace so that newer, preemption-aware
> > userspace could opt back in if it properly supported preemption.
> > 
> > For gen11, there shouldn't be any "old" userspace around that doesn't
> > support preemption, so shouldn't the kernel just leave object-level
> > preemption enabled by default (meaning there's no need to expose this
> > register to userspace to allow it to explicitly opt-in)?
> 
> Makes sense to me. We should have known by know if somebody expects to
> control the register, because they would be failing to do so.
> 
> Mesa could also drop the register load for Gen11+
> 
> Regards, Joonas

+ Rafael, as he's done all the preemption work in Mesa.

That seems reasonable to me.  It looks like i965 always enables
mid-object preemption (sets CS_CHICKEN1 bit 0) on Gen10+, and never
disables it.  You can probably safely turn it on by default, and we
can stop writing the register altogether.

Thanks for the heads up!

--Ken
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