[Intel-gfx] [PATCH 3/4] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3/4 wakeup time

[José Roberto de Souza]

A new field with the training pattern(TP) wakeup time for PSR2 was
added to VBT, so lets use it when available otherwise it will
fallback to PSR1 wakeup time.

BSpec: 20131

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  8 ++++++++
 drivers/gpu/drm/i915/intel_bios.c     | 10 ++++++++++
 drivers/gpu/drm/i915/intel_psr.c      |  2 +-
 drivers/gpu/drm/i915/intel_vbt_defs.h |  3 +++
 4 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d9893d35f0e2..e739ed9ce60c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -967,6 +967,13 @@ enum psr_tp_wakeup_time {
 	PSR_TP_WAKEUP_TIME_LAST
 };
 
+enum psr2_tp_wakeup_time {
+	PSR2_TP_WAKEUP_TIME_500USEC = 0,
+	PSR2_TP_WAKEUP_TIME_100USEC,
+	PSR2_TP_WAKEUP_TIME_2500USEC,
+	PSR2_TP_WAKEUP_TIME_50USEC
+};
+
 struct intel_vbt_data {
 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1005,6 +1012,7 @@ struct intel_vbt_data {
 		enum psr_lines_to_wait lines_to_wait;
 		enum psr_tp_wakeup_time tp1_wakeup_time;
 		enum psr_tp_wakeup_time tp2_tp3_tp4_wakeup_time;
+		enum psr2_tp_wakeup_time psr2_tp2_tp3_tp4_wakeup_time;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 6de6f6f1deec..23130e0d5e6c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -757,6 +757,16 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 
 		dev_priv->vbt.psr.tp2_tp3_tp4_wakeup_time = wakeup_time;
 	}
+
+	if (bdb->version >= 226) {
+		u32 wakeup_time = psr_table->psr2_tp2_tp3_tp4_wakeup_time;
+
+		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+		dev_priv->vbt.psr.psr2_tp2_tp3_tp4_wakeup_time = wakeup_time;
+	} else {
+		/* Reusing PSR1 wakeup time for PSR2 in older VBTs */
+		dev_priv->vbt.psr.psr2_tp2_tp3_tp4_wakeup_time = dev_priv->vbt.psr.tp2_tp3_tp4_wakeup_time;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5daf0b9e2b42..2fc537fb6e78 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -494,7 +494,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	val |= dev_priv->vbt.psr.tp2_tp3_tp4_wakeup_time << EDP_PSR2_TP2_TP3_TIME_SHIFT;
+	val |= dev_priv->vbt.psr.psr2_tp2_tp3_tp4_wakeup_time << EDP_PSR2_TP2_TP3_TIME_SHIFT;
 
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 4ed66efde49f..dc0a14977953 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -772,6 +772,9 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_tp4_wakeup_time;
+
+	/* PSR2 TP2/TP3/TP4 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_tp4_wakeup_time;
 } __packed;
 
 struct bdb_psr {
-- 
2.20.1