[Intel-gfx] [PATCH] drm/i915/icl: do a posting read after irq install

[Mika Kuoppala]

Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> writes:

> On 1/22/2019 6:32 PM, Daniele Ceraolo Spurio wrote:
>> When reading GEN11_GT_INTR_DWx closely after enabling the interrupts
>> in gen11_irq_postinstall, the returned value is garbage. This can
>
> To clarify, this only happens (or at least I've only seen it) during 
> runtime_resume.
>

How did you notice?

> Daniele
>
>> cause other parts of the setup code (e.g. gen11_reset_one_iir) to
>> think that there are interrupts to be cleared when there are none.
>>
>> The garbage value is only seen on the first read done after the enable,
>> so this looks like a posting issue. Adding a posting read after enabling
>> the interrupts does indeed fix the problem.
>>
>> Note that the posting read has been purposely added outside of
>> gen11_master_intr_enable since the issue has only been observed when the
>> full interrupt setup is performed.

Scary enough that maybe it would have been warranted inside it. But
well we know where to escalate if it shows up elsewhere.

Acked-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

>>
>> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_irq.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 5fd5080c4ccb..7056ae2d1e0e 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -4089,6 +4089,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
>>   	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>>   
>>   	gen11_master_intr_enable(dev_priv->regs);
>> +	POSTING_READ(GEN11_GFX_MSTR_IRQ);
>>   
>>   	return 0;
>>   }