[Intel-gfx] [PATCH v8 1/7] drm/i915: initialize unused MOCS entries to PTE

[Lucas De Marchi]

On Wed, Jan 23, 2019 at 07:33:35PM +0100, Tomasz Lis wrote:
>
>
>On 2019-01-22 06:12, Lucas De Marchi wrote:
>>Instead of initializing them to uncached, let's set them to PTE for
>>kernel tracking. While at it do some minor adjustments to comments and
>>coding style.
>>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>Reviewed-by: Tomasz Lis <tomasz.lis at intel.com>

thanks

>One comment (with no expectations for change) below.

>>+		*cs++ = table->table[I915_MOCS_PTE].control_value;
>Entries from enum i915_mocs_table_index are not guaranteed to mean the 
>same thing in future gens;
>but for the time, that will work. And later it might still work, we 
>don't know.


I thought about this, but these values are part of the kernel API
(the same thing could be said for the first entry, btw).

If/when they don't make sense anymore we would need to remap them to
entry that makes sense.

Lucas De Marchi

>-Tomasz
>>  	}
>>  	*cs++ = MI_NOOP;
>>@@ -345,7 +336,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
>>  	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2);
>>-	for (i = 0; i < table->size/2; i++) {
>>+	for (i = 0; i < table->size / 2; i++) {
>>  		*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
>>  		*cs++ = l3cc_combine(table, 2 * i, 2 * i + 1);
>>  	}
>>@@ -353,18 +344,18 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
>>  	if (table->size & 0x01) {
>>  		/* Odd table size - 1 left over */
>>  		*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
>>-		*cs++ = l3cc_combine(table, 2 * i, 0);
>>+		*cs++ = l3cc_combine(table, 2 * i, I915_MOCS_PTE);
>>  		i++;
>>  	}
>>  	/*
>>-	 * Now set the rest of the table to uncached - use entry 0 as
>>-	 * this will be uncached. Leave the last pair uninitialised as
>>-	 * they are reserved by the hardware.
>>+	 * Now set the unused entries to PTE. These entries are officially
>>+	 * undefined and no contract for the contents and settings is given
>>+	 * for these entries.
>>  	 */
>>  	for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
>>  		*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
>>-		*cs++ = l3cc_combine(table, 0, 0);
>>+		*cs++ = l3cc_combine(table, I915_MOCS_PTE, I915_MOCS_PTE);
>>  	}
>>  	*cs++ = MI_NOOP;
>>@@ -395,22 +386,21 @@ void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
>>  	if (!get_mocs_settings(dev_priv, &table))
>>  		return;
>>-	for (i = 0; i < table.size/2; i++)
>>-		I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1));
>>+	for (i = 0; i < table.size / 2; i++)
>>+		I915_WRITE(GEN9_LNCFCMOCS(i),
>>+			   l3cc_combine(&table, 2 * i, 2 * i + 1));
>>  	/* Odd table size - 1 left over */
>>  	if (table.size & 0x01) {
>>-		I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0));
>>+		I915_WRITE(GEN9_LNCFCMOCS(i),
>>+			   l3cc_combine(&table, 2 * i, I915_MOCS_PTE));
>>  		i++;
>>  	}
>>-	/*
>>-	 * Now set the rest of the table to uncached - use entry 0 as
>>-	 * this will be uncached. Leave the last pair as initialised as
>>-	 * they are reserved by the hardware.
>>-	 */
>>+	/* Now set the rest of the table to PTE */
>>  	for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
>>-		I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));
>>+		I915_WRITE(GEN9_LNCFCMOCS(i),
>>+			   l3cc_combine(&table, I915_MOCS_PTE, I915_MOCS_PTE));
>>  }
>>  /**
>