[Intel-gfx] [PATCH 1/5] drm/i915/icl: use tc_port in MG_PLL macros
Paulo Zanoni
paulo.r.zanoni at intel.com
Thu Jan 24 01:15:26 UTC 2019
Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
> Fix the TODO leftover in the code by changing the argument in MG_PLL
> macros. The MG_PLL ids used to access the register values can be
> converted from tc_port rather than port.
>
An explanation on why the new model is better would be amazing. It may
be obvious to you, but it's not to other people.
> The helper functions were also renamed to use "tc" as prefix to make
> them more generic.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++---------
> drivers/gpu/drm/i915/intel_ddi.c | 7 ++-
> drivers/gpu/drm/i915/intel_display.c | 3 +-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 79 +++++++++++++--------------
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
> 5 files changed, 72 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9a1340cfda6c..de209e0fdc01 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9545,7 +9545,7 @@ enum skl_power_gate {
> #define _MG_PLL3_ENABLE 0x46038
> #define _MG_PLL4_ENABLE 0x4603C
> /* Bits are the same as DPLL0_ENABLE */
> -#define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
> +#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
> _MG_PLL2_ENABLE)
>
> #define _MG_REFCLKIN_CTL_PORT1 0x16892C
> @@ -9554,9 +9554,9 @@ enum skl_power_gate {
> #define _MG_REFCLKIN_CTL_PORT4 0x16B92C
> #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
> #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
> -#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
> - _MG_REFCLKIN_CTL_PORT1, \
> - _MG_REFCLKIN_CTL_PORT2)
> +#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
> + _MG_REFCLKIN_CTL_PORT1, \
> + _MG_REFCLKIN_CTL_PORT2)
>
> #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
> #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
> @@ -9566,9 +9566,9 @@ enum skl_power_gate {
> #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
> #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
> #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
> -#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
> - _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> - _MG_CLKTOP2_CORECLKCTL1_PORT2)
> +#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
> + _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> + _MG_CLKTOP2_CORECLKCTL1_PORT2)
>
> #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
> #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
> @@ -9586,9 +9586,9 @@ enum skl_power_gate {
> #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
> #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
> #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
> -#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
> - _MG_CLKTOP2_HSCLKCTL_PORT1, \
> - _MG_CLKTOP2_HSCLKCTL_PORT2)
> +#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
> + _MG_CLKTOP2_HSCLKCTL_PORT1, \
> + _MG_CLKTOP2_HSCLKCTL_PORT2)
>
> #define _MG_PLL_DIV0_PORT1 0x168A00
> #define _MG_PLL_DIV0_PORT2 0x169A00
> @@ -9600,8 +9600,8 @@ enum skl_power_gate {
> #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
> #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
> #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
> -#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \
> - _MG_PLL_DIV0_PORT2)
> +#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
> + _MG_PLL_DIV0_PORT2)
>
> #define _MG_PLL_DIV1_PORT1 0x168A04
> #define _MG_PLL_DIV1_PORT2 0x169A04
> @@ -9615,8 +9615,8 @@ enum skl_power_gate {
> #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
> #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
> #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
> -#define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \
> - _MG_PLL_DIV1_PORT2)
> +#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
> + _MG_PLL_DIV1_PORT2)
>
> #define _MG_PLL_LF_PORT1 0x168A08
> #define _MG_PLL_LF_PORT2 0x169A08
> @@ -9628,8 +9628,8 @@ enum skl_power_gate {
> #define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
> #define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
> #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
> -#define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_LF_PORT1, \
> - _MG_PLL_LF_PORT2)
> +#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
> + _MG_PLL_LF_PORT2)
>
> #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
> #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
> @@ -9641,9 +9641,9 @@ enum skl_power_gate {
> #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
> #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
> #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
> -#define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \
> - _MG_PLL_FRAC_LOCK_PORT1, \
> - _MG_PLL_FRAC_LOCK_PORT2)
> +#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
> + _MG_PLL_FRAC_LOCK_PORT1, \
> + _MG_PLL_FRAC_LOCK_PORT2)
>
> #define _MG_PLL_SSC_PORT1 0x168A10
> #define _MG_PLL_SSC_PORT2 0x169A10
> @@ -9655,8 +9655,8 @@ enum skl_power_gate {
> #define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
> #define MG_PLL_SSC_FLLEN (1 << 9)
> #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
> -#define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_SSC_PORT1, \
> - _MG_PLL_SSC_PORT2)
> +#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
> + _MG_PLL_SSC_PORT2)
>
> #define _MG_PLL_BIAS_PORT1 0x168A14
> #define _MG_PLL_BIAS_PORT2 0x169A14
> @@ -9675,8 +9675,8 @@ enum skl_power_gate {
> #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
> #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
> #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
> -#define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \
> - _MG_PLL_BIAS_PORT2)
> +#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
> + _MG_PLL_BIAS_PORT2)
>
> #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
> #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
> @@ -9687,9 +9687,9 @@ enum skl_power_gate {
> #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
> #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
> #define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
> -#define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \
> - _MG_PLL_TDC_COLDST_BIAS_PORT1, \
> - _MG_PLL_TDC_COLDST_BIAS_PORT2)
> +#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
> + _MG_PLL_TDC_COLDST_BIAS_PORT1, \
> + _MG_PLL_TDC_COLDST_BIAS_PORT2)
>
> #define _CNL_DPLL0_CFGCR0 0x6C000
> #define _CNL_DPLL1_CFGCR0 0x6C080
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ce44744a5f9d..8dbf6c9e22fb 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1391,16 +1391,17 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
> static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
> enum port port)
> {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> u32 mg_pll_div0, mg_clktop_hsclkctl;
> u32 m1, m2_int, m2_frac, div1, div2, refclk;
> u64 tmp;
>
> refclk = dev_priv->cdclk.hw.ref;
>
> - mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
> - mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
> + mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
> + mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
>
> - m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
> + m1 = I915_READ(MG_PLL_DIV1(tc_port)) & MG_PLL_DIV1_FBPREDIV_MASK;
> m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
> m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
> (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 62d61fcad89c..a5de70e6bf59 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9415,7 +9415,8 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
> if (WARN_ON(!intel_dpll_is_combophy(id)))
> return;
> } else if (intel_port_is_tc(dev_priv, port)) {
> - id = icl_port_to_mg_pll_id(port);
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + id = icl_tc_port_to_pll_id(tc_port);
Checkpatch's complaint makes sense here. You could also opt to simply
to:
id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
> } else {
> WARN(1, "Invalid port %x\n", port);
> return;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 606f54dde086..211b3ffa5bed 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2639,14 +2639,14 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> return link_clock;
> }
>
> -static enum port icl_mg_pll_id_to_port(enum intel_dpll_id id)
> +static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
> {
> - return id - DPLL_ID_ICL_MGPLL1 + PORT_C;
> + return id - DPLL_ID_ICL_MGPLL1;
> }
>
> -enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
> +enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
> {
> - return port - PORT_C + DPLL_ID_ICL_MGPLL1;
> + return tc_port + DPLL_ID_ICL_MGPLL1;
> }
The "_mg_" in the name was supposed to help callers easily realize that
these functions don't make sense without mg plls. I kinda liked them,
especially in the first case where you can pass any id, which would
result in wrong code.
So, one of my fears is that there may be other patches in-flight which
touch these registers and will silently make our code use port again.
The cherry on top of this patch would be to put those enums inside
single-element structs in a way that would make gcc complain when you
accessed one instead of the other (including inside macros). Feel free
to implement this if you like the idea.
With the checkpatch error addressed and the improved commit message:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> bool intel_dpll_is_combophy(enum intel_dpll_id id)
> @@ -2925,7 +2925,10 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> ret = icl_calc_dpll_state(crtc_state, encoder, clock,
> &pll_state);
> } else {
> - min = icl_port_to_mg_pll_id(port);
> + enum tc_port tc_port;
> +
> + tc_port = intel_port_to_tc(dev_priv, port);
> + min = icl_tc_port_to_pll_id(tc_port);
> max = min;
> ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
> &pll_state);
> @@ -2959,12 +2962,8 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
> return CNL_DPLL_ENABLE(id);
> else if (id == DPLL_ID_ICL_TBTPLL)
> return TBT_PLL_ENABLE;
> - else
> - /*
> - * TODO: Make MG_PLL macros use
> - * tc port id instead of port id
> - */
> - return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
> +
> + return MG_PLL_ENABLE(icl_pll_id_to_tc_port(id));
> }
>
> static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -2974,7 +2973,6 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> const enum intel_dpll_id id = pll->info->id;
> intel_wakeref_t wakeref;
> bool ret = false;
> - enum port port;
> u32 val;
>
> wakeref = intel_display_power_get_if_enabled(dev_priv,
> @@ -2991,32 +2989,33 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> } else {
> - port = icl_mg_pll_id_to_port(id);
> - hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
> + enum tc_port tc_port = icl_pll_id_to_tc_port(id);
> +
> + hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port));
> hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
>
> hw_state->mg_clktop2_coreclkctl1 =
> - I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
> + I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
> hw_state->mg_clktop2_coreclkctl1 &=
> MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
>
> hw_state->mg_clktop2_hsclkctl =
> - I915_READ(MG_CLKTOP2_HSCLKCTL(port));
> + I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
> hw_state->mg_clktop2_hsclkctl &=
> MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
> MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
> MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
> MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
>
> - hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
> - hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));
> - hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));
> - hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
> - hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));
> + hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
> + hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));
> + hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port));
> + hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port));
> + hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port));
>
> - hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));
> + hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port));
> hw_state->mg_pll_tdc_coldst_bias =
> - I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
> + I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
>
> if (dev_priv->cdclk.hw.ref == 38400) {
> hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
> @@ -3051,7 +3050,7 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
> - enum port port = icl_mg_pll_id_to_port(pll->info->id);
> + enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> u32 val;
>
> /*
> @@ -3060,41 +3059,41 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
> * during the calc/readout phase if the mask depends on some other HW
> * state like refclk, see icl_calc_mg_pll_state().
> */
> - val = I915_READ(MG_REFCLKIN_CTL(port));
> + val = I915_READ(MG_REFCLKIN_CTL(tc_port));
> val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
> val |= hw_state->mg_refclkin_ctl;
> - I915_WRITE(MG_REFCLKIN_CTL(port), val);
> + I915_WRITE(MG_REFCLKIN_CTL(tc_port), val);
>
> - val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
> + val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
> val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
> val |= hw_state->mg_clktop2_coreclkctl1;
> - I915_WRITE(MG_CLKTOP2_CORECLKCTL1(port), val);
> + I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val);
>
> - val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
> + val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
> val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
> MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
> MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
> MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
> val |= hw_state->mg_clktop2_hsclkctl;
> - I915_WRITE(MG_CLKTOP2_HSCLKCTL(port), val);
> + I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val);
>
> - I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0);
> - I915_WRITE(MG_PLL_DIV1(port), hw_state->mg_pll_div1);
> - I915_WRITE(MG_PLL_LF(port), hw_state->mg_pll_lf);
> - I915_WRITE(MG_PLL_FRAC_LOCK(port), hw_state->mg_pll_frac_lock);
> - I915_WRITE(MG_PLL_SSC(port), hw_state->mg_pll_ssc);
> + I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
> + I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
> + I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
> + I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock);
> + I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
>
> - val = I915_READ(MG_PLL_BIAS(port));
> + val = I915_READ(MG_PLL_BIAS(tc_port));
> val &= ~hw_state->mg_pll_bias_mask;
> val |= hw_state->mg_pll_bias;
> - I915_WRITE(MG_PLL_BIAS(port), val);
> + I915_WRITE(MG_PLL_BIAS(tc_port), val);
>
> - val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
> + val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
> val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
> val |= hw_state->mg_pll_tdc_coldst_bias;
> - I915_WRITE(MG_PLL_TDC_COLDST_BIAS(port), val);
> + I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val);
>
> - POSTING_READ(MG_PLL_TDC_COLDST_BIAS(port));
> + POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
> }
>
> static void icl_pll_enable(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index e96e79413b54..40e8391a92f2 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -344,7 +344,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> u32 pll_id);
> int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> -enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
> +enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> bool intel_dpll_is_combophy(enum intel_dpll_id id);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
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