[Intel-gfx] [PATCH 3/5] drm/i915/icl: remove dpll from clk_sel

[Paulo Zanoni]

Em qui, 2019-01-17 às 12:21 -0800, Lucas De Marchi escreveu:
> We should not pass DPLL_ID_ICL_DPLL0 or DPLL_ID_ICL_DPLL1 to this
> function because the path is only taken for non-combophy ports. Let the
> warning trigger if improper value is given.
> 
> While at it, rename the function to match the register name we are
> trying to program.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 4dc03e8c6c10..94d0fdc14b42 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -995,7 +995,7 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
>  	}
>  }
>  
> -static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> +static uint32_t icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
>  				       const struct intel_crtc_state *crtc_state)
>  {
>  	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> @@ -1004,10 +1004,11 @@ static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
>  
>  	switch (id) {
>  	default:
> +		/*
> +		 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be use

s/use/used/

With that:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> +		 * here, so do warn if this get passed in
> +		 */
>  		MISSING_CASE(id);
> -		/* fall through */
> -	case DPLL_ID_ICL_DPLL0:
> -	case DPLL_ID_ICL_DPLL1:
>  		return DDI_CLK_SEL_NONE;
>  	case DPLL_ID_ICL_TBTPLL:
>  		switch (clock) {
> @@ -2869,7 +2870,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  	if (IS_ICELAKE(dev_priv)) {
>  		if (!intel_port_is_combophy(dev_priv, port))
>  			I915_WRITE(DDI_CLK_SEL(port),
> -				   icl_pll_to_ddi_pll_sel(encoder, crtc_state));
> +				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
>  		val = I915_READ(DPCLKA_CFGCR0);