[Intel-gfx] [PATCH v4 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just pick the limit to match the render
engine max stride (256KiB).

No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
remapping on gen2/3 due extra complications from fence alignment
and gen2 2KiB GTT tile size. Also no real benefit since the
display engine limits already match the other limits.

v2: Rebase due to is_ccs_modifier()
v3: Tweak the comment and commit msg

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3713b6f1796e..e0cf43336b62 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2470,6 +2470,15 @@ static
 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
 			u32 pixel_format, u64 modifier)
 {
+	/*
+	 * Arbitrary limit for gen4+ chosen to match the
+	 * render engine max stride.
+	 *
+	 * The new CCS hash mode makes remapping impossible
+	 */
+	if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
+		return 256*1024;
+
 	return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
 }
 
-- 
2.19.2