[Intel-gfx] [PATCH v2] drm/i915: Don't use the second dbuf slice on icl

[Mahesh Kumar]

LGTM...

Reviewed-by: Mahesh Kumar <mahesh1.sh.kumar at gmail.com>

On Wed, Jan 30, 2019 at 9:21 PM Ville Syrjala
<ville.syrjala at linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> The code managing the dbuf slices is borked and needs some
> real work to fix. In the meantime let's just stop using the
> second slice.
>
> v2: Drop the change to intel_enabled_dbuf_slices_num() (Mahesh)
>
> Cc: Mahesh Kumar <mahesh1.sh.kumar at gmail.com>
> Reviewed-by: Imre Deak <imre.deak at intel.com> #v1
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 53b706154c94..ed9786241307 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3822,8 +3822,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
>
>         /*
>          * 12GB/s is maximum BW supported by single DBuf slice.
> +        *
> +        * FIXME dbuf slice code is broken:
> +        * - must wait for planes to stop using the slice before powering it off
> +        * - plane straddling both slices is illegal in multi-pipe scenarios
> +        * - should validate we stay within the hw bandwidth limits
>          */
> -       if (num_active > 1 || total_data_bw >= GBps(12)) {
> +       if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
>                 ddb->enabled_slices = 2;
>         } else {
>                 ddb->enabled_slices = 1;
> --
> 2.19.2
>