[Intel-gfx] [PATCH 04/15] drm/i915/dsb: Added enum for reg write capability.

[Animesh Manna]

DSB can access specific register, To identify those register
which can be written through DSB, enum reg_write_cap is added
to hold the capability.

Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Signed-off-by: Animesh Manna <animesh.manna at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..b2e8349f3295 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,11 +178,22 @@
  */
 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
 
+/*
+ * Added enum to hold the capability for those registers which can be written
+ * through DSB.
+ */
+enum reg_write_cap {
+	MMIO_WRITE,
+	DSB_WRITE,
+	DSB_INDEX_WRITE
+};
+
 typedef struct {
 	u32 reg;
+	enum reg_write_cap cap;
 } i915_reg_t;
 
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__})
 
 #define INVALID_MMIO_REG _MMIO(0)
 
-- 
2.21.0