[Intel-gfx] [PATCH 0/4] MCR fixes

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

A few bugs in programming the MCR register sneaked in past review.

First of all fls() usage is wrong and suffers from off-by-one problem.

Secondly the assert in WaProgramMgsrForL3BankSpecificMmioReads is also wrong
due inverted logic.

With MCR programming fixed we can stop ignoring the engine workarounds
verification of GEN8_L3SQCREG4.

Tvrtko Ursulin (4):
  drm/i915: Fix GEN8_MCR_SELECTOR programming
  drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
  drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
  drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4

 drivers/gpu/drm/i915/gt/intel_engine_cs.c   | 19 --------
 drivers/gpu/drm/i915/gt/intel_sseu.c        | 24 ++++++++++
 drivers/gpu/drm/i915/gt/intel_sseu.h        |  2 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 53 ++++++++-------------
 drivers/gpu/drm/i915/i915_drv.h             |  2 -
 5 files changed, 45 insertions(+), 55 deletions(-)

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2.20.1