[Intel-gfx] [PATCH] drm/i915: Fix wrong escape clock divisor init for GLK

[Maarten Lankhorst]

Op 10-07-2019 om 16:12 schreef Stanislav Lisovskiy:
> According to Bspec clock divisor registers in GeminiLake
> should be initialized by shifting 1(<<) to amount of correspondent
> divisor. While i915 was writing all this time that value as is.
>
> Surprisingly that it by accident worked, until we met some issues
> with Microtech Etab.
>
> Signed-off-by: Stanislav.Lisovskiy at intel.com
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108826
> ---
>  drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> index 99cc3e2e9c2c..f016a776a39e 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> @@ -396,8 +396,8 @@ static void glk_dsi_program_esc_clock(struct drm_device *dev,
>  	else
>  		txesc2_div = 10;
>  
> -	I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
> -	I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
> +	I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
> +	I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
>  }
>  
>  /* Program BXT Mipi clocks and dividers */

Missing a fixes tag?

find the original commit that introduced this, then run dim fixes $commitid.

Cheers,

Maarten