[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev7)

[Patchwork]

== Series Details ==

Series: Initial support for Tiger Lake (rev7)
URL   : https://patchwork.freedesktop.org/series/62726/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3b308280d186 drm/i915: Add 4th pipe and transcoder
22ff20d71578 drm/i915/tgl: add initial Tiger Lake definitions
2983d1e70483 drm/i915/tgl: Introduce Tiger Lake PCH
7149b1effb99 drm/i915/tgl: Add TGL PCH detection in virtualized environment
0df93c01c401 drm/i915/tgl: Add TGL PCI IDs
-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#34: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#34: FILE: include/drm/i915_pciids.h:587:
+#define INTEL_TGL_12_IDS(info) \
+	INTEL_VGA_DEVICE(0x9A49, info), \
+	INTEL_VGA_DEVICE(0x9A40, info), \
+	INTEL_VGA_DEVICE(0x9A59, info), \
+	INTEL_VGA_DEVICE(0x9A60, info), \
+	INTEL_VGA_DEVICE(0x9A68, info), \
+	INTEL_VGA_DEVICE(0x9A70, info), \
+	INTEL_VGA_DEVICE(0x9A78, info)

total: 1 errors, 0 warnings, 1 checks, 21 lines checked
2f8ef50027bf drm/i915/tgl: Check if pipe D is fused
94eba30b3e6c drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use on transcoder A
bf8ff2c09217 drm/i915/tgl: Add power well support
2989b1102dc2 drm/i915/tgl: Add power well to support 4th pipe
d7400914c2ff drm/i915/tgl: Add new pll ids
22c6e15f27f6 drm/i915/tgl: Add pll manager
debae094a188 drm/i915/tgl: Add additional ports for Tiger Lake
0778c4f497cd drm/i915/tgl: Add additional PHYs for Tiger Lake
2eb2a6413434 drm/i915/tgl: init ddi port A-C for Tiger Lake
65cdba68fd27 drm/i915/tgl: apply Display WA #1178 to fix type C dongles
22c07d339ead drm/i915/gen12: MBUS B credit change
be190cc98460 drm/i915/tgl: Add gmbus gpio pin to port mapping
3e56d7286d31 drm/i915/tgl: port to ddc pin mapping
e0bdb26890c9 drm/i915/tgl: Add vbt value mapping for DDC Bus pin
3f6b9b8e3306 drm/i915/tgl: Add DPLL registers
542373bf46c5 drm/i915/tgl: Update DPLL clock reference register