[Intel-gfx] [PATCH v3 15/21] drm/i915/tgl: apply Display WA #1178 to fix type C dongles

[Matt Roper]

On Thu, Jul 11, 2019 at 10:31:09AM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h                    | 4 +++-
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 12aa9ce08d95..061432862c7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  	int pw_idx = power_well->desc->hsw.idx;
>  	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
>  	u32 val;
> +	int wa_idx_max;
>  
>  	val = I915_READ(regs->driver);
>  	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> @@ -462,6 +463,12 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  
>  	hsw_wait_for_power_well_enable(dev_priv, power_well);
>  
> +	/* Display WA #1178: icl, tgl */
> +	if (IS_TIGERLAKE(dev_priv))
> +		wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
> +	else
> +		wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
> +
>  	/* Display WA #1178: icl */
>  	if (IS_ICELAKE(dev_priv) &&

I think this needs to change to !ehl now.

>  	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&

And this should use your new wa_idx_max variable


Matt

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ca70be40a467..ad96c5b4975c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9244,9 +9244,11 @@ enum skl_power_gate {
>  #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
>  #define _ICL_AUX_ANAOVRD1_A		0x162398
>  #define _ICL_AUX_ANAOVRD1_B		0x6C398
> +#define _TGL_AUX_ANAOVRD1_C		0x160398
>  #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
>  						    _ICL_AUX_ANAOVRD1_A, \
> -						    _ICL_AUX_ANAOVRD1_B))
> +						    _ICL_AUX_ANAOVRD1_B, \
> +						    _TGL_AUX_ANAOVRD1_C))
>  #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
>  #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
>  
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795