[Intel-gfx] [PATCH] drm/i915/tgl: apply Display WA #1178 to fix type C dongles

[Matt Roper]

On Thu, Jul 11, 2019 at 02:35:17PM -0700, Lucas De Marchi wrote:
> Add port C to workaround to cover Tiger Lake.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-22-lucas.demarchi@intel.com

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 12 +++++++++---
>  drivers/gpu/drm/i915/i915_reg.h                    |  4 +++-
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 12aa9ce08d95..d25fd5a25199 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -453,6 +453,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  	int pw_idx = power_well->desc->hsw.idx;
>  	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
>  	u32 val;
> +	int wa_idx_max;
>  
>  	val = I915_READ(regs->driver);
>  	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> @@ -462,9 +463,14 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>  
>  	hsw_wait_for_power_well_enable(dev_priv, power_well);
>  
> -	/* Display WA #1178: icl */
> -	if (IS_ICELAKE(dev_priv) &&
> -	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
> +	/* Display WA #1178: icl, tgl */
> +	if (IS_TIGERLAKE(dev_priv))
> +		wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
> +	else
> +		wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
> +
> +	if (!IS_ELKHARTLAKE(dev_priv) &&
> +	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
>  	    !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
>  		val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
>  		val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b1a6628199e4..a8e2e05e7d7e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9274,9 +9274,11 @@ enum skl_power_gate {
>  #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
>  #define _ICL_AUX_ANAOVRD1_A		0x162398
>  #define _ICL_AUX_ANAOVRD1_B		0x6C398
> +#define _TGL_AUX_ANAOVRD1_C		0x160398
>  #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
>  						    _ICL_AUX_ANAOVRD1_A, \
> -						    _ICL_AUX_ANAOVRD1_B))
> +						    _ICL_AUX_ANAOVRD1_B, \
> +						    _TGL_AUX_ANAOVRD1_C))
>  #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
>  #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
>  
> -- 
> 2.21.0
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795