[Intel-gfx] [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl

[Shankar, Uma]

>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Tuesday, July 2, 2019 9:49 AM
>To: intel-gfx at lists.freedesktop.org
>Cc: ville.syrjala at linux.intel.com; Nikula, Jani <jani.nikula at intel.com>; Shankar, Uma
><uma.shankar at intel.com>; Kulkarni, Vandita <vandita.kulkarni at intel.com>
>Subject: [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
>
>Rest of the latency programming remains same as that of ICL.

You can put this as "latency programming for TGL remains same as that of ICL and EHL.
Extended the same for TGL"

With this minor nit fixed.
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

>Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>b/drivers/gpu/drm/i915/display/icl_dsi.c
>index 556eba2636fe..e3980676bcef 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -404,8 +404,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
>intel_encoder *encoder)
> 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> 		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>
>-		/* For EHL set latency optimization for PCS_DW1 lanes */
>-		if (IS_ELKHARTLAKE(dev_priv)) {
>+		/* EHL and TGL, set latency optimization for PCS_DW1 lanes */
>+		if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
> 			tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
> 			tmp &= ~LATENCY_OPTIM_MASK;
> 			tmp |= LATENCY_OPTIM_VAL(0);
>--
>2.21.0.5.gaeb582a