[Intel-gfx] [PATCH v2 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info.

[Anshuman Gupta]

This patch exposes DC3CO counter in i915_dmc_info debugfs.
Which will be useful for DC3CO validation.
DMC firmware is using DMC_DEBUG3 register as DC3CO counter
register on TGL, but as per B.Specs DMC_DEBUG3 is general
purpose register.

Cc: jani.nikula at intel.com
Cc: imre.deak at intel.com
Cc: animesh.manna at intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++++-
 drivers/gpu/drm/i915/i915_reg.h     | 3 +++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4d59972e9689..b382b0b9e430 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2504,9 +2504,16 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
-	if (WARN_ON(INTEL_GEN(dev_priv) > 11))
+	if (WARN_ON(INTEL_GEN(dev_priv) > 12))
 		goto out;
 
+	/*
+	 * B.Spes specify that DMC_DEBUG3 is general debug register
+	 * DMC folks uses this register for DC3CO counter for TGL
+	 */
+	if (IS_TIGERLAKE(dev_priv))
+		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
 	seq_printf(m, "DC3 -> DC5 count: %d\n",
 		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
 						    SKL_CSR_DC3_DC5_COUNT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df36d84a7a8d..68e4b78e4a64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7265,6 +7265,9 @@ enum {
 #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 
+/* DMC DEBUG COUNTERS for TGL*/
+#define DMC_DEBUG3		_MMIO(0x101090) /*DC3CO debug counter*/
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.21.0