[Intel-gfx] [PATCH v2 10/10] drm/i915/tgl:Added new DC5/DC6 counter.

[Anshuman Gupta]

TGL onwards we have new DC5 and DC6 counter
DMC_DEBUG1 and DMC_DEBUG2, these counter will retain
there values upon DMC reset.

Cc: jani.nikula at intel.com
Cc: imre.deak at intel.com
Cc: animesh.manna at intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 +++++---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b382b0b9e430..fa09d93c639a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2515,11 +2515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n",
-		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
-						    SKL_CSR_DC3_DC5_COUNT));
+		   I915_READ(IS_TIGERLAKE(dev_priv) ? DMC_DEBUG1 :
+			     (IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
+						    SKL_CSR_DC3_DC5_COUNT)));
 	if (!IS_GEN9_LP(dev_priv))
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
-			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+			   I915_READ(IS_TIGERLAKE(dev_priv) ? DMC_DEBUG2 :
+				     SKL_CSR_DC5_DC6_COUNT));
 
 out:
 	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68e4b78e4a64..5e567bd4f820 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7266,6 +7266,8 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 
 /* DMC DEBUG COUNTERS for TGL*/
+#define DMC_DEBUG1		_MMIO(0x101084)
+#define DMC_DEBUG2		_MMIO(0x101088)
 #define DMC_DEBUG3		_MMIO(0x101090) /*DC3CO debug counter*/
 
 /* interrupts */
-- 
2.21.0