[Intel-gfx] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Sasha Levin]

Hi,

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.2.1, v5.1.18, v4.19.59, v4.14.133, v4.9.185, v4.4.185.

v5.2.1: Failed to apply! Possible dependencies:
    Unable to calculate

v5.1.18: Failed to apply! Possible dependencies:
    Unable to calculate

v4.19.59: Failed to apply! Possible dependencies:
    Unable to calculate

v4.14.133: Failed to apply! Possible dependencies:
    9c61de4c69a2 ("drm/i915: Consolidate max_cdclk_freq check in intel_crtc_compute_min_cdclk()")
    c8dae55a8ced ("drm/i915/vlv: Add cdclk workaround for DSI")
    d305e0614601 ("drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"")

v4.9.185: Failed to apply! Possible dependencies:
    294591cfbd2b ("drm/i915: Update kerneldoc for intel_dpll_mgr.c")
    2c42e5351445 ("drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state")
    3c0fb58820ac ("drm/i915: Rename intel_shared_dpll_commit() to _swap_state()")
    47a6bc61b866 ("drm/i915: Move broxton phy code to intel_dpio_phy.c")
    7ff89ca21358 ("drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c")
    842d416654eb ("drm/i915: Create a struct to hold information about the broxton phys")
    8cbeb06dc6b5 ("drm/i915: Implement cdclk restrictions based on Azalia BCLK")
    a1c414ee82d9 ("drm/i915: Introduce intel_release_shared_dpll()")
    b284eedaf74b ("drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()")
    b6e08203cc1f ("drm/i915: Move broxton vswing sequence to intel_dpio_phy.c")
    c8dae55a8ced ("drm/i915/vlv: Add cdclk workaround for DSI")
    ed37892e6df2 ("drm/i915: Address broxton phy registers based on phy and channel number")
    f38861b814b5 ("drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c")

v4.4.185: Failed to apply! Possible dependencies:
    12fda3876d08 ("drm/i915/ibx: Ensure the HW is powered during PLL HW readout")
    22cba31bae9d ("Documentation/sphinx: add basic working Sphinx configuration and build")
    294591cfbd2b ("drm/i915: Update kerneldoc for intel_dpll_mgr.c")
    64e1077a1f93 ("drm/i915: Clean up eDP PLL state asserts")
    7abd4b35a577 ("drm/i915: Move shared dpll code to a new file")
    7ff89ca21358 ("drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c")
    87ad321287ae ("drm/i915: add onoff utility function")
    8cbeb06dc6b5 ("drm/i915: Implement cdclk restrictions based on Azalia BCLK")
    c8dae55a8ced ("drm/i915/vlv: Add cdclk workaround for DSI")
    ca00c2b986ea ("Documentation/gpu: split up the gpu documentation")
    cb597fcea5c2 ("Documentation/gpu: add new gpu.rst converted from DocBook gpu.tmpl")
    f169660ed4e5 ("drm/i915/dp: Add a standalone function to obtain shared dpll for HSW/BDW/SKL/BXT")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

--
Thanks,
Sasha