[Intel-gfx] [PATCH 08/22] drm/i915/tgl: Add DKL phy pll registers

[Atwood, Matthew S]

On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni <vandita.kulkarni at intel.com>
> 
> These are the registers needed to program Dekel PHY. Some register
> definitions reuse the MG PHY definitions. Add a comment on those so
> we
> don't need to duplicate the functions for programming them.
> 
Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 94
> +++++++++++++++++++++++++++++++++
>  1 file changed, 94 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 41c8b40eebd5..70872c9391ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10026,6 +10026,100 @@ enum skl_power_gate {
>  						   _TGL_DPLL1_CFGCR1, \
>  						   _TGL_TBTPLL_CFGCR1)
>  
> +#define _DKL_PHY1_BASE			0x168000
> +#define _DKL_PHY2_BASE			0x169000
> +#define _DKL_PHY3_BASE			0x16A000
> +#define _DKL_PHY4_BASE			0x16B000
> +#define _DKL_PHY5_BASE			0x16C000
> +#define _DKL_PHY6_BASE			0x16D000
> +
> +/* DEKEL PHY MMIO Address = Phy base + (internal address &
> ~index_mask) */
> +#define _DKL_PLL_DIV0			0x200
> +#define   DKL_PLL_DIV0_INTEG_COEFF(x)	((x) << 16)
> +#define   DKL_PLL_DIV0_INTEG_COEFF_MASK	(0x1F << 16)
> +#define   DKL_PLL_DIV0_PROP_COEFF(x)	((x) << 12)
> +#define   DKL_PLL_DIV0_PROP_COEFF_MASK	(0xF << 12)
> +#define   DKL_PLL_DIV0_FBPREDIV(x)	((x) << 8)
> +#define   DKL_PLL_DIV0_FBPREDIV_MASK	(0xF << 8)
> +#define   DKL_PLL_DIV0_FBDIV_INT(x)	((x) << 0)
> +#define   DKL_PLL_DIV0_FBDIV_INT_MASK	(0xFF << 0)
> +#define DKL_PLL_DIV0(tc_port)		_MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> +						    _DKL_PHY2_BASE) + \
> +						    _DKL_PLL_DIV0)
> +
> +#define _DKL_PLL_DIV1				0x204
> +#define   DKL_PLL_DIV1_IREF_TRIM(x)		((x) << 16)
> +#define   DKL_PLL_DIV1_IREF_TRIM_MASK		(0x1F << 16)
> +#define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)	((x) << 0)
> +#define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK	(0xFF << 0)
> +#define DKL_PLL_DIV1(tc_port)		_MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> +						    _DKL_PHY2_BASE) + \
> +						    _DKL_PLL_DIV1)
> +
> +#define _DKL_PLL_SSC				0x210
> +#define   DKL_PLL_SSC_IREF_NDIV_RATIO(x)	((x) << 29)
> +#define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK	(0x7 << 29)
> +#define   DKL_PLL_SSC_STEP_LEN(x)		((x) << 16)
> +#define   DKL_PLL_SSC_STEP_LEN_MASK		(0xFF << 16)
> +#define   DKL_PLL_SSC_STEP_NUM(x)		((x) << 11)
> +#define   DKL_PLL_SSC_STEP_NUM_MASK		(0x7 << 11)
> +#define   DKL_PLL_SSC_EN			(1 << 9)
> +#define DKL_PLL_SSC(tc_port)		_MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> +						    _DKL_PHY2_BASE) + \
> +						    _DKL_PLL_SSC)
> +
> +#define _DKL_PLL_BIAS			0x214
> +#define   DKL_PLL_BIAS_FRAC_EN_H	(1 << 30)
> +#define   DKL_PLL_BIAS_FBDIV_FRAC(x)	((x) << 8)
> +#define   DKL_PLL_BIAS_FBDIV_FRAC_MASK	(0xFF << 8)
> +#define DKL_PLL_BIAS(tc_port)		_MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> +						    _DKL_PHY2_BASE) + \
> +						    _DKL_PLL_BIAS)
> +
> +#define _DKL_PLL_TDC_COLDST_BIAS		0x218
> +#define   DKL_PLL_TDC_SSC_STEP_SIZE(x)		((x) << 8)
> +#define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK	(0xFF << 8)
> +#define   DKL_PLL_TDC_FEED_FWD_GAIN(x)		((x) << 0)
> +#define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK	(0xFF << 0)
> +#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
> +						     _DKL_PHY1_BASE, \
> +						     _DKL_PHY2_BASE) +
> \
> +						     _DKL_PLL_TDC_COLDS
> T_BIAS)
> +
> +#define _DKL_REFCLKIN_CTL		0x12C
> +/* Bits are the same as MG_REFCLKIN_CTL */
> +#define DKL_REFCLKIN_CTL(tc_port)	_MMIO(_PORT(tc_port, \
> +						    _DKL_PHY1_BASE, \
> +						    _DKL_PHY2_BASE) + \
> +					      _DKL_REFCLKIN_CTL)
> +
> +#define _DKL_CLKTOP2_HSCLKCTL		0xD4
> +/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
> +#define DKL_CLKTOP2_HSCLKCTL(tc_port)	_MMIO(_PORT(tc_port, \
> +						    _DKL_PHY1_BASE, \
> +						    _DKL_PHY2_BASE) + \
> +					      _DKL_CLKTOP2_HSCLKCTL)
> +
> +#define _DKL_CLKTOP2_CORECLKCTL1		0xD8
> +/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
> +#define DKL_CLKTOP2_CORECLKCTL1(tc_port)	_MMIO(_PORT(tc_port, \
> +							    _DKL_PHY1_B
> ASE, \
> +							    _DKL_PHY2_B
> ASE) + \
> +						      _DKL_CLKTOP2_CORE
> CLKCTL1)
> +
> +/*
> + * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has
> more than
> + * 4KB of register space, so a separate index is programmed in
> HIP_INDEX_REG0
> + * or HIP_INDEX_REG1, based on the port number, to set the upper 2
> address
> + * bits that point the 4KB window into the full PHY register space.
> + */
> +#define _HIP_INDEX_REG0		0x1010A0
> +#define _HIP_INDEX_REG1		0x1010A4
> +#define HIP_INDEX_REG(tc_port)	_MMIO((tc_port) < 3 \
> +				      ? _HIP_INDEX_REG0 \
> +				      : _HIP_INDEX_REG1)
> +#define HIP_INDEX_VAL(index, tc_port)	((index) << (((tc_port)
> * 8) % 32))
> +
>  /* BXT display engine PLL */
>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
>  #define   BXT_DE_PLL_RATIO(x)		(x)	/*
> {60,65,100} * 19.2MHz */